98 lines
3.9 KiB
Plaintext
98 lines
3.9 KiB
Plaintext
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/*
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* arch/arm/boot/dts/panel-s-wuxga-8-0-mods.dtsi
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*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <dt-bindings/display/tegra-dc.h>
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#include <dt-bindings/display/tegra-panel.h>
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/ {
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host1x {
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dsi {
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panel_s_wuxga_8_0_mods: panel-s-wuxga-8-0-mods {
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status = "disabled";
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compatible = "s,wuxga-8-0-mods";
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nvidia,dsi-instance = <DSI_INSTANCE_0>;
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nvidia,dsi-n-data-lanes = <8>;
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nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
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nvidia,dsi-refresh-rate = <60>;
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nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
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nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>;
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nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE>;
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nvidia,dsi-ganged-type = <TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT>;
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nvidia,dsi-ganged-swap-links = <1>;
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nvidia,dsi-ganged-write-to-all-links = <1>;
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nvidia,dsi-controller-vs = <DSI_VS_1>;
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nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
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nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
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nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
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nvidia,dsi-suspend-stop-stream-late = <TEGRA_DSI_ENABLE>;
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nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
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nvidia,default_color_space = <1>; /*default color profile:adobeRGB*/
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nvidia,dsi-init-cmd =
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/* Long Packet: <PACKETTYPE[u8] COMMANDID[u8] PAYLOADCOUNT[u16] ECC[u8] PAYLOAD[..] CHECKSUM[u16]> */
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/* Short Packet: <PACKETTYPE[u8] COMMANDID[u8] DATA0[u8] DATA1[u8] ECC[u8]> */
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/* For DSI packets each DT cell is interpreted as u8 not u32 */
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>,
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/* This panel has a very sensitive power on/off sequence.
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* Send a few more frames for safety. No max limit from vendor. */
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<TEGRA_DSI_SEND_FRAME 10>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>;
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nvidia,dsi-n-init-cmd = <3>;
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nvidia,dsi-suspend-cmd =
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_OFF 0x0 0x0>,
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<TEGRA_DSI_SEND_FRAME 3>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_ENTER_SLEEP_MODE 0x0 0x0>,
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<TEGRA_DSI_SEND_FRAME 10>;
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nvidia,dsi-n-suspend-cmd = <4>;
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nvidia,dsi-pkt-seq =
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<CMD_VS LEN_SHORT PKT_LP LINE_STOP>,
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<CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
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<CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
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<CMD_HS LEN_SHORT CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>,
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<CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
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<CMD_HS LEN_SHORT CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>;
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disp-default-out {
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nvidia,out-type = <TEGRA_DC_OUT_DSI>;
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nvidia,out-width = <107>;
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nvidia,out-height = <172>;
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nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
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nvidia,out-parent-clk = "pll_d";
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nvidia,out-xres = <4096>;
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nvidia,out-yres = <2160>;
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};
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display-timings {
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1920x1080-32 {
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clock-frequency = <148500000>;
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hactive = <1920>;
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vactive = <1080>;
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hfront-porch = <88>;
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hback-porch = <148>;
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hsync-len = <44>;
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vfront-porch = <4>;
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vback-porch = <36>;
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vsync-len = <5>;
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nvidia,h-ref-to-sync = <1>;
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nvidia,v-ref-to-sync = <1>;
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};
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};
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};
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};
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};
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};
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