44 lines
2.0 KiB
C
44 lines
2.0 KiB
C
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/*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _DT_BINDINGS_PINCTRL_TEGRA_PADCTL_PHY_H
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#define _DT_BINDINGS_PINCTRL_TEGRA_PADCTL_PHY_H 1
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/* 0-15 for USB3 */
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#define TEGRA_PADCTL_PHY_USB3_BASE (0)
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#define TEGRA_PADCTL_PHY_USB3_P(x) ((x) + TEGRA_PADCTL_PHY_USB3_BASE)
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/* 16-31 for UTMI */
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#define TEGRA_PADCTL_PHY_UTMI_BASE (16)
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#define TEGRA_PADCTL_PHY_UTMI_P(x) ((x) + TEGRA_PADCTL_PHY_UTMI_BASE)
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/* 32-47 for HSIC */
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#define TEGRA_PADCTL_PHY_HSIC_BASE (32)
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#define TEGRA_PADCTL_PHY_HSIC_P(x) ((x) + TEGRA_PADCTL_PHY_HSIC_BASE)
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/* 48-63 for Tegra built-in CDP phy for UTMI */
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#define TEGRA_PADCTL_PHY_CDP_BASE (48)
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#define TEGRA_PADCTL_PHY_CDP_P(x) ((x) + TEGRA_PADCTL_PHY_CDP_BASE)
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#define TEGRA_PADCTL_PORT_DISABLED (0)
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#define TEGRA_PADCTL_PORT_HOST_ONLY (1)
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#define TEGRA_PADCTL_PORT_DEVICE_ONLY (2)
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#define TEGRA_PADCTL_PORT_OTG_CAP (3)
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#endif /* _DT_BINDINGS_PINCTRL_TEGRA_PADCTL_PHY_H */
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