65 lines
2.4 KiB
C
65 lines
2.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Definitions for Jetson tegra186-p3509-0000-p3636-0001 board.
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*
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* Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#include <dt-bindings/gpio/tegra186-gpio.h>
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#define JETSON_COMPATIBLE "nvidia,p3509-0000+p3636-0001"
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/* SoC function name for clock signal on 40-pin header pin 7 */
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#define HDR40_CLK "aud"
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/* SoC function name for I2S interface on 40-pin header pins 12, 35, 38 and 40 */
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#define HDR40_I2S "i2s1"
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/* SoC function name for SPI interface on 40-pin header pins 19, 21, 23, and 24 */
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#define HDR40_SPI "spi1"
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/* SoC function name for UART interface on 40-pin header pins 8, 10, 11 and 36 */
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#define HDR40_UART "uartc"
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/* SoC function name for touch clock signal on 40-pin header pin 31 */
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#define HDR40_TOUCH "touch"
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/* SoC pin name definitions for 40-pin header */
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#define HDR40_PIN7 "aud_mclk_pj4"
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#define HDR40_PIN11 "uart3_rts_pw4"
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#define HDR40_PIN12 "dap1_sclk_pj0"
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#define HDR40_PIN13 "gpio_sen1_pv1"
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#define HDR40_PIN18 "gpio_sen4_pv4"
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#define HDR40_PIN19 "gpio_wan7_ph2"
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#define HDR40_PIN21 "gpio_wan6_ph1"
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#define HDR40_PIN22 "gpio_sen2_pv2"
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#define HDR40_PIN23 "gpio_wan5_ph0"
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#define HDR40_PIN24 "gpio_wan8_ph3"
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#define HDR40_PIN29 "gpio_cam2_pn1"
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#define HDR40_PIN31 "touch_clk_pee2"
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#define HDR40_PIN32 "gpio_dis0_pu0"
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#define HDR40_PIN33 "gpio_dis5_pu5"
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#define HDR40_PIN35 "dap1_fs_pj3"
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#define HDR40_PIN36 "uart3_cts_pw5"
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#define HDR40_PIN37 "gpio_sen3_pv3"
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#define HDR40_PIN38 "dap1_din_pj2"
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#define HDR40_PIN40 "dap1_dout_pj1"
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/* SoC GPIO definitions for 40-pin header */
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#define HDR40_PIN7_GPIO TEGRA_MAIN_GPIO(J, 4)
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#define HDR40_PIN11_GPIO TEGRA_MAIN_GPIO(W, 4)
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#define HDR40_PIN12_GPIO TEGRA_MAIN_GPIO(J, 0)
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#define HDR40_PIN13_GPIO TEGRA_MAIN_GPIO(V, 1)
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#define HDR40_PIN18_GPIO TEGRA_MAIN_GPIO(V, 4)
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#define HDR40_PIN19_GPIO TEGRA_MAIN_GPIO(H, 2)
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#define HDR40_PIN21_GPIO TEGRA_MAIN_GPIO(H, 1)
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#define HDR40_PIN22_GPIO TEGRA_MAIN_GPIO(V, 2)
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#define HDR40_PIN23_GPIO TEGRA_MAIN_GPIO(H, 0)
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#define HDR40_PIN24_GPIO TEGRA_MAIN_GPIO(H, 3)
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#define HDR40_PIN29_GPIO TEGRA_MAIN_GPIO(N, 1)
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#define HDR40_PIN31_GPIO TEGRA_AON_GPIO(EE, 2)
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#define HDR40_PIN32_GPIO TEGRA_MAIN_GPIO(U, 0)
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#define HDR40_PIN33_GPIO TEGRA_MAIN_GPIO(U, 5)
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#define HDR40_PIN35_GPIO TEGRA_MAIN_GPIO(J, 3)
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#define HDR40_PIN36_GPIO TEGRA_MAIN_GPIO(W, 5)
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#define HDR40_PIN37_GPIO TEGRA_MAIN_GPIO(V, 3)
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#define HDR40_PIN38_GPIO TEGRA_MAIN_GPIO(J, 2)
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#define HDR40_PIN40_GPIO TEGRA_MAIN_GPIO(J, 1)
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