464 lines
17 KiB
Plaintext
464 lines
17 KiB
Plaintext
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What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Enable/disable tracing on this specific trace entiry.
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Enabling a source implies the source has been configured
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properly and a sink has been identidifed for it. The path
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of coresight components linking the source to the sink is
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configured and managed automatically by the coresight framework.
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What: /sys/bus/coresight/devices/<memory_map>.etm/cpu
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) The CPU this tracing entity is associated with.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of PE comparator inputs that are
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available for tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of address comparator pairs that are
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available for tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of counters that are available for
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tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates how many external inputs are implemented.
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What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of Context ID comparators that are
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available for tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of VMID comparators that are available
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for tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of sequencer states that are
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implemented.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of resource selection pairs that are
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available for tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of single-shot comparator controls that
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are available for tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/reset
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (W) Cancels all configuration on a trace unit and set it back
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to its boot configuration.
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What: /sys/bus/coresight/devices/<memory_map>.etm/mode
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls various modes supported by this ETM, for example
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P0 instruction tracing, branch broadcast, cycle counting and
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context ID tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/pe
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls which PE to trace.
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What: /sys/bus/coresight/devices/<memory_map>.etm/event
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3.
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What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls the behavior of the events in bank 0 to 3.
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What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls the insertion of global timestamps in the trace
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streams.
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What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls how often trace synchronization requests occur.
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What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Sets the threshold value for cycle counting.
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What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls which regions in the memory map are enabled to
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use branch broadcasting.
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What: /sys/bus/coresight/devices/<memory_map>.etm/event_vinst
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls instruction trace filtering.
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What: /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) In Secure state, each bit controls whether instruction
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tracing is enabled for the corresponding exception level.
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What: /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) In non-secure state, each bit controls whether instruction
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tracing is enabled for the corresponding exception level.
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What: /sys/bus/coresight/devices/<memory_map>.etm/addr_idx
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Select which address comparator or pair (of comparators) to
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work with.
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What: /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls what type of comparison the trace unit performs.
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What: /sys/bus/coresight/devices/<memory_map>.etm/addr_single
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used to setup single address comparator values.
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What: /sys/bus/coresight/devices/<memory_map>.etm/addr_range
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used to setup address range comparator values.
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What: /sys/bus/coresight/devices/<memory_map>.etm/seq_idx
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Select which sequensor.
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What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Use this to set, or read, the sequencer state.
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What: /sys/bus/coresight/devices/<memory_map>.etm/seq_event
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Moves the sequencer state to a specific state.
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What: /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Moves the sequencer to state 0 when a programmed event
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occurs.
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What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Select which counter unit to work with.
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What: /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) This sets or returns the reload count value of the
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specific counter.
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What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_val
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) This sets or returns the current count value of the
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specific counter.
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What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls the operation of the selected counter.
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What: /sys/bus/coresight/devices/<memory_map>.etm/res_idx
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Select which resource selection unit to work with.
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What: /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls the selection of the resources in the trace unit.
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What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Select which context ID comparator to work with.
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What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Get/Set the context ID comparator value to trigger on.
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What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Mask for all 8 context ID comparator value
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registers (if implemented).
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What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Select which virtual machine ID comparator to work with.
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What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_val
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Get/Set the virtual machine ID comparator value to
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trigger on.
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What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Mask for all 8 virtual machine ID comparator value
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registers (if implemented).
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What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Print the content of the OS Lock Status Register (0x304).
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The value it taken directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Print the content of the Power Down Control Register
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(0x310). The value is taken directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Print the content of the Power Down Status Register
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(0x314). The value is taken directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Print the content of the SW Lock Status Register
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(0xFB4). The value is taken directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Print the content of the Authentication Status Register
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(0xFB8). The value is taken directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Print the content of the Device ID Register
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(0xFC8). The value is taken directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Print the content of the Device Type Register
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|
|
(0xFCC). The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Print the content of the Peripheral ID0 Register
|
||
|
|
(0xFE0). The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Print the content of the Peripheral ID1 Register
|
||
|
|
(0xFE4). The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Print the content of the Peripheral ID2 Register
|
||
|
|
(0xFE8). The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Print the content of the Peripheral ID3 Register
|
||
|
|
(0xFEC). The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig
|
||
|
|
Date: February 2016
|
||
|
|
KernelVersion: 4.07
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Print the content of the trace configuration register
|
||
|
|
(0x010) as currently set by SW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid
|
||
|
|
Date: February 2016
|
||
|
|
KernelVersion: 4.07
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Print the content of the trace ID register (0x040).
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Returns the tracing capabilities of the trace unit (0x1E0).
|
||
|
|
The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Returns the tracing capabilities of the trace unit (0x1E4).
|
||
|
|
The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Returns the maximum size of the data value, data address,
|
||
|
|
VMID, context ID and instuction address in the trace unit
|
||
|
|
(0x1E8). The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Returns the value associated with various resources
|
||
|
|
available to the trace unit. See the Trace Macrocell
|
||
|
|
architecture specification for more details (0x1E8).
|
||
|
|
The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Returns how many resources the trace unit supports (0x1F0).
|
||
|
|
The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Returns how many resources the trace unit supports (0x1F4).
|
||
|
|
The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Returns the maximum speculation depth of the instruction
|
||
|
|
trace stream. (0x180). The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Returns the number of P0 right-hand keys that the trace unit
|
||
|
|
can use (0x184). The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Returns the number of P1 right-hand keys that the trace unit
|
||
|
|
can use (0x188). The value is taken directly from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Returns the number of special P1 right-hand keys that the
|
||
|
|
trace unit can use (0x18C). The value is taken directly from
|
||
|
|
the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Returns the number of conditional P1 right-hand keys that
|
||
|
|
the trace unit can use (0x190). The value is taken directly
|
||
|
|
from the HW.
|
||
|
|
|
||
|
|
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13
|
||
|
|
Date: April 2015
|
||
|
|
KernelVersion: 4.01
|
||
|
|
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||
|
|
Description: (R) Returns the number of special conditional P1 right-hand keys
|
||
|
|
that the trace unit can use (0x194). The value is taken
|
||
|
|
directly from the HW.
|