61 lines
2.0 KiB
Plaintext
61 lines
2.0 KiB
Plaintext
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UniPhier outer cache controller
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UniPhier SoCs are integrated with a full-custom outer cache controller system.
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All of them have a level 2 cache controller, and some have a level 3 cache
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controller as well.
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Required properties:
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- compatible: should be "socionext,uniphier-system-cache"
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- reg: offsets and lengths of the register sets for the device. It should
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contain 3 regions: control register, revision register, operation register,
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in this order.
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- cache-unified: specifies the cache is a unified cache.
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- cache-size: specifies the size in bytes of the cache
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- cache-sets: specifies the number of associativity sets of the cache
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- cache-line-size: specifies the line size in bytes
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- cache-level: specifies the level in the cache hierarchy. The value should
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be 2 for L2 cache, 3 for L3 cache, etc.
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Optional properties:
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- next-level-cache: phandle to the next level cache if present. The next level
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cache should be also compatible with "socionext,uniphier-system-cache".
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The L2 cache must exist to use the L3 cache; the cache hierarchy must be
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indicated correctly with "next-level-cache" properties.
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Example 1 (system with L2):
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
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<0x506c0000 0x400>;
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cache-unified;
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cache-size = <0x80000>;
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cache-sets = <256>;
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cache-line-size = <128>;
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cache-level = <2>;
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};
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Example 2 (system with L2 and L3):
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
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<0x506c0000 0x400>;
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cache-unified;
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cache-size = <0x200000>;
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cache-sets = <512>;
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cache-line-size = <128>;
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cache-level = <2>;
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next-level-cache = <&l3>;
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};
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l3: l3-cache@500c8000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
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<0x506c8000 0x400>;
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cache-unified;
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cache-size = <0x400000>;
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cache-sets = <512>;
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cache-line-size = <256>;
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cache-level = <3>;
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};
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