46 lines
1.4 KiB
Plaintext
46 lines
1.4 KiB
Plaintext
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NVIDIA Tegra ACONNECT Bus
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The Tegra ACONNECT bus is an AXI switch which is used to connnect various
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components inside the Audio Processing Engine (APE). All CPU accesses to
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the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
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Required properties:
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- compatible: Must be "nvidia,tegra210-aconnect".
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- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
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and APE interface clock (TEGRA210_CLK_APB2APE).
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- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
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'clocks' entries.
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- power-domains: Must contain a phandle that points to the audio powergate
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(namely 'aud') for Tegra210.
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- #address-cells: The number of cells used to represent physical base addresses
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in the aconnect address space. Should be 1.
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- #size-cells: The number of cells used to represent the size of an address
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range in the aconnect address space. Should be 1.
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- ranges: Mapping of the aconnect address space to the CPU address space.
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All devices accessed via the ACONNNECT are described by child-nodes.
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Example:
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aconnect@702c0000 {
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compatible = "nvidia,tegra210-aconnect";
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clocks = <&tegra_car TEGRA210_CLK_APE>,
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<&tegra_car TEGRA210_CLK_APB2APE>;
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clock-names = "ape", "apb2ape";
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power-domains = <&pd_audio>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
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status = "disabled";
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child1 {
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...
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};
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child2 {
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...
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};
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};
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