105 lines
3.7 KiB
Plaintext
105 lines
3.7 KiB
Plaintext
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* Renesas R-Car (RZ/G) DMA Controller Device Tree bindings
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Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA
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controller instances named DMAC capable of serving multiple clients. Channels
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can be dedicated to specific clients or shared between a large number of
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clients.
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Each DMA client is connected to one dedicated port of the DMAC, identified by
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an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
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256 clients in total. When the number of hardware channels is lower than the
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number of clients to be served, channels must be shared between multiple DMA
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clients. The association of DMA clients to DMAC channels is fully dynamic and
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not described in these device tree bindings.
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Required Properties:
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- compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
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Examples with soctypes are:
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- "renesas,dmac-r8a7743" (RZ/G1M)
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- "renesas,dmac-r8a7745" (RZ/G1E)
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- "renesas,dmac-r8a7790" (R-Car H2)
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- "renesas,dmac-r8a7791" (R-Car M2-W)
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- "renesas,dmac-r8a7792" (R-Car V2H)
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- "renesas,dmac-r8a7793" (R-Car M2-N)
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- "renesas,dmac-r8a7794" (R-Car E2)
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- "renesas,dmac-r8a7795" (R-Car H3)
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- reg: base address and length of the registers block for the DMAC
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- interrupts: interrupt specifiers for the DMAC, one for each entry in
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interrupt-names.
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- interrupt-names: one entry per channel, named "ch%u", where %u is the
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channel number ranging from zero to the number of channels minus one.
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- clock-names: "fck" for the functional clock
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- clocks: a list of phandle + clock-specifier pairs, one for each entry
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in clock-names.
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- clock-names: must contain "fck" for the functional clock.
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- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
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connected to the DMA client
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- dma-channels: number of DMA channels
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Example: R8A7790 (R-Car H2) SYS-DMACs
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x20000>;
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interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
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0 200 IRQ_TYPE_LEVEL_HIGH
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0 201 IRQ_TYPE_LEVEL_HIGH
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0 202 IRQ_TYPE_LEVEL_HIGH
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0 203 IRQ_TYPE_LEVEL_HIGH
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0 204 IRQ_TYPE_LEVEL_HIGH
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0 205 IRQ_TYPE_LEVEL_HIGH
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0 206 IRQ_TYPE_LEVEL_HIGH
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0 207 IRQ_TYPE_LEVEL_HIGH
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0 208 IRQ_TYPE_LEVEL_HIGH
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0 209 IRQ_TYPE_LEVEL_HIGH
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0 210 IRQ_TYPE_LEVEL_HIGH
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0 211 IRQ_TYPE_LEVEL_HIGH
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0 212 IRQ_TYPE_LEVEL_HIGH
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0 213 IRQ_TYPE_LEVEL_HIGH
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0 214 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
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clock-names = "fck";
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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dmac1: dma-controller@e6720000 {
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compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
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reg = <0 0xe6720000 0 0x20000>;
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interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
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0 216 IRQ_TYPE_LEVEL_HIGH
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0 217 IRQ_TYPE_LEVEL_HIGH
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0 218 IRQ_TYPE_LEVEL_HIGH
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0 219 IRQ_TYPE_LEVEL_HIGH
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0 308 IRQ_TYPE_LEVEL_HIGH
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0 309 IRQ_TYPE_LEVEL_HIGH
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0 310 IRQ_TYPE_LEVEL_HIGH
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0 311 IRQ_TYPE_LEVEL_HIGH
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0 312 IRQ_TYPE_LEVEL_HIGH
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0 313 IRQ_TYPE_LEVEL_HIGH
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0 314 IRQ_TYPE_LEVEL_HIGH
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0 315 IRQ_TYPE_LEVEL_HIGH
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0 316 IRQ_TYPE_LEVEL_HIGH
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0 317 IRQ_TYPE_LEVEL_HIGH
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0 318 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
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clock-names = "fck";
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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