41 lines
1.5 KiB
Plaintext
41 lines
1.5 KiB
Plaintext
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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
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Required properties:
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- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
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must contain "nvidia,tegra30-efuse". For Tegra114, must contain
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"nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
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Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where
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<chip> is tegra132.
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Details:
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nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
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due to a hardware bug. Tegra20 also lacks certain information which is
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available in later generations such as fab code, lot code, wafer id,..
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nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
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The differences between these SoCs are the size of the efuse array,
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the location of the spare (OEM programmable) bits and the location of
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the speedo data.
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- reg: Should contain 1 entry: the entry gives the physical address and length
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of the fuse registers.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- fuse
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- fuse
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Example:
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fuse@7000f800 {
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compatible = "nvidia,tegra20-efuse";
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reg = <0x7000f800 0x400>,
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<0x70000000 0x400>;
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clocks = <&tegra_car TEGRA20_CLK_FUSE>;
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clock-names = "fuse";
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resets = <&tegra_car 39>;
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reset-names = "fuse";
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};
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