47 lines
1.3 KiB
Plaintext
47 lines
1.3 KiB
Plaintext
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* ARC-HS Interrupt Distribution Unit
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This optional 2nd level interrupt controller can be used in SMP configurations for
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dynamic IRQ routing, load balancing of common/external IRQs towards core intc.
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Properties:
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- compatible: "snps,archs-idu-intc"
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- interrupt-controller: This is an interrupt controller.
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- interrupt-parent: <reference to parent core intc>
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- #interrupt-cells: Must be <2>.
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- interrupts: <...> specifies the upstream core irqs
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First cell specifies the "common" IRQ from peripheral to IDU
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Second cell specifies the irq distribution mode to cores
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0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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intc accessed via the special ARC AUX register interface, hence "reg" property
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is not specified.
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Example:
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core_intc: core-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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/*
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* <hwirq distribution>
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* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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*/
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#interrupt-cells = <2>;
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/* upstream core irqs: downstream these are "COMMON" irq 0,1.. */
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interrupts = <24 25 26 27 28 29 30 31>;
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};
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some_device: serial@c0fc1000 {
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interrupt-parent = <&idu_intc>;
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interrupts = <0 0>; /* upstream idu IRQ #24, Round Robin */
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};
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