62 lines
2.7 KiB
Plaintext
62 lines
2.7 KiB
Plaintext
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* Freescale i.MX6 PCIe interface
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This PCIe host controller is based on the Synopsis Designware PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie"
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- reg: base address and length of the PCIe controller
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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- "msi": The interrupt that is asserted when an MSI is received
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- clock-names: Must include the following additional entries:
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- "pcie_phy"
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Optional properties:
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- fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
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- fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
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- fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20
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- fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127
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- fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127
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- fsl,max-link-speed: Specify PCI gen for link capability. Must be '2' for
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gen2, otherwise will default to gen1. Note that the IMX6 LVDS clock outputs
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do not meet gen2 jitter requirements and thus for gen2 capability a gen2
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compliant clock generator should be used and configured.
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- reset-gpio: Should specify the GPIO for controlling the PCI bus device reset
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signal. It's not polarity aware and defaults to active-low reset sequence
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(L=reset state, H=operation state).
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- reset-gpio-active-high: If present then the reset sequence using the GPIO
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specified in the "reset-gpio" property is reversed (H=reset state,
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L=operation state).
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Additional required properties for imx6sx-pcie:
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- clock names: Must include the following additional entries:
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- "pcie_inbound_axi"
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Example:
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pcie@0x01000000 {
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compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
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reg = <0x01ffc000 0x04000>,
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<0x01f00000 0x80000>;
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reg-names = "dbi", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
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0x81000000 0 0 0x01f80000 0 0x00010000
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0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
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num-lanes = <1>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 144>, <&clks 206>, <&clks 189>;
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clock-names = "pcie", "pcie_bus", "pcie_phy";
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};
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