73 lines
3.6 KiB
Plaintext
73 lines
3.6 KiB
Plaintext
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Tegra SOC USB PHY
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The device node for Tegra SOC USB PHY:
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Required properties :
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- compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
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For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
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"nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
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tegra114, tegra124, tegra132, or tegra210.
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- reg : Defines the following set of registers, in the order listed:
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- The PHY's own register set.
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Always present.
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- The register set of the PHY containing the UTMI pad control registers.
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Present if-and-only-if phy_type == utmi.
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- phy_type : Should be one of "utmi", "ulpi" or "hsic".
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- clocks : Defines the clocks listed in the clock-names property.
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- clock-names : The following clock names must be present:
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- reg: The clock needed to access the PHY's own registers. This is the
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associated EHCI controller's clock. Always present.
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- pll_u: PLL_U. Always present.
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- timer: The timeout clock (clk_m). Present if phy_type == utmi.
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- utmi-pads: The clock needed to access the UTMI pad control registers.
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Present if phy_type == utmi.
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- ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
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Present if phy_type == ulpi, and ULPI link mode is in use.
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Must include the following entries:
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- usb: The PHY's own reset signal.
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- utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control
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registers. Required even if phy_type == ulpi.
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Required properties for phy_type == ulpi:
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- nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
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Required PHY timing params for utmi phy, for all chips:
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- nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
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start of sync launches RxActive
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- nvidia,elastic-limit : Variable FIFO Depth of elastic input store
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- nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
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before declare IDLE.
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- nvidia,term-range-adj : Range adjusment on terminations
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- Either one of the following for HS driver output control:
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- nvidia,xcvr-setup : integer, uses the provided value.
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- nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read
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from the on-chip fuses
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If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.
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- nvidia,xcvr-lsfslew : LS falling slew rate control.
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- nvidia,xcvr-lsrslew : LS rising slew rate control.
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Required PHY timing params for utmi phy, only on Tegra30 and above:
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- nvidia,xcvr-hsslew : HS slew rate control.
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- nvidia,hssquelch-level : HS squelch detector level.
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- nvidia,hsdiscon-level : HS disconnect detector level.
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Optional properties:
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- nvidia,has-legacy-mode : boolean indicates whether this controller can
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operate in legacy mode (as APX 2500 / 2600). In legacy mode some
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registers are accessed through the APB_MISC base address instead of
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the USB controller.
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- nvidia,is-wired : boolean. Indicates whether we can do certain kind of power
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optimizations for the devices that are always connected. e.g. modem.
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- dr_mode : dual role mode. Indicates the working mode for the PHY. Can be
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"host", "peripheral", or "otg". Defaults to "host" if not defined.
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host means this is a host controller
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peripheral means it is device controller
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otg means it can operate as either ("on the go")
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- nvidia,has-utmi-pad-registers : boolean indicates whether this controller
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contains the UTMI pad control registers common to all USB controllers.
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VBUS control (required for dr_mode == otg, optional for dr_mode == host):
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- vbus-supply: regulator for VBUS
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