49 lines
1.4 KiB
Plaintext
49 lines
1.4 KiB
Plaintext
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Tegra SoC DFLL PWM controller
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Required properties:
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- compatible: For Tegra210, must contain "nvidia,tegra210-dfll-pwm".
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- reg: physical base address and length of the controller's registers
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- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
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the cells format.
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- clock-names: Must include the "ref" entry.
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- clocks: Must contain one entry, for the DFLL closed loop reference clock.
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See ../clocks/clock-bindings.txt for details.
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- pwm-regulator: phandle to PWM regulator for using this PWM controller.
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- pinctrl-names: Must contain two entries to enable and disable PWM signals
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output pinmux states.
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- pinctrl-0: pinmux state to enable PWM signals output
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- pinctrl-1: pinmux state to disable PWM signals output
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Example:
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pinmux: pinmux@700008d4 {
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dvfs_pwm_active_state: dvfs_pwm_active {
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dvfs_pwm_pbb1 {
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nvidia,pins = "dvfs_pwm_pbb1";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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};
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dvfs_pwm_inactive_state: dvfs_pwm_inactive {
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dvfs_pwm_pbb1 {
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nvidia,pins = "dvfs_pwm_pbb1";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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};
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};
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pwm_dfll: pwm@70110000 {
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compatible = "nvidia,tegra210-dfll-pwm";
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reg = <0x0 0x70110000 0x0 0x400>;
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clocks = <&tegra_car TEGRA210_CLK_DFLL_REF>;
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clock-names = "ref";
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#pwm-cells = <2>;
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pwm-regulator = <&cpu_ovr_reg>;
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pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
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pinctrl-0 = <&dvfs_pwm_active_state>;
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pinctrl-1 = <&dvfs_pwm_inactive_state>;
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status = "okay";
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};
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