53 lines
1.9 KiB
Plaintext
53 lines
1.9 KiB
Plaintext
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Freescale FlexTimer Module (FTM) PWM controller
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The same FTM PWM device can have a different endianness on different SoCs. The
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device tree provides a property to describing this so that an operating system
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device driver can handle all variants of the device. Refer to the table below
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for the endianness of the FTM PWM block as integrated into the existing SoCs:
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SoC | FTM-PWM endianness
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--------+-------------------
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Vybrid | LE
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LS1 | BE
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LS2 | LE
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Please see ../regmap/regmap.txt for more detail about how to specify endian
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modes in device tree.
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Required properties:
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- compatible: Should be "fsl,vf610-ftm-pwm".
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- reg: Physical base address and length of the controller's registers
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- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
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the cells format.
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- clock-names: Should include the following module clock source entries:
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"ftm_sys" (module clock, also can be used as counter clock),
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"ftm_ext" (external counter clock),
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"ftm_fix" (fixed counter clock),
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"ftm_cnt_clk_en" (external and fixed counter clock enable/disable).
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- clocks: Must contain a phandle and clock specifier for each entry in
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clock-names, please see clock/clock-bindings.txt for details of the property
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values.
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- pinctrl-names: Must contain a "default" entry.
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- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
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See pinctrl/pinctrl-bindings.txt for details of the property values.
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- big-endian: Boolean property, required if the FTM PWM registers use a big-
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endian rather than little-endian layout.
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Example:
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pwm0: pwm@40038000 {
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compatible = "fsl,vf610-ftm-pwm";
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reg = <0x40038000 0x1000>;
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#pwm-cells = <3>;
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clock-names = "ftm_sys", "ftm_ext",
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"ftm_fix", "ftm_cnt_clk_en";
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clocks = <&clks VF610_CLK_FTM0>,
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<&clks VF610_CLK_FTM0_EXT_SEL>,
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<&clks VF610_CLK_FTM0_FIX_SEL>,
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<&clks VF610_CLK_FTM0_EXT_FIX_EN>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm0_1>;
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big-endian;
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};
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