89 lines
3.3 KiB
Plaintext
89 lines
3.3 KiB
Plaintext
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* HiSilicon SAS controller
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The HiSilicon SAS controller supports SAS/SATA.
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Main node required properties:
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- compatible : value should be as follows:
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(a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
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(b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
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- sas-addr : array of 8 bytes for host SAS address
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- reg : Address and length of the SAS register
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- hisilicon,sas-syscon: phandle of syscon used for sas control
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- ctrl-reset-reg : offset to controller reset register in ctrl reg
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- ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
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- ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
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- queue-count : number of delivery and completion queues in the controller
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- phy-count : number of phys accessible by the controller
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- interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal
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sources; the interrupts are ordered in 3 groups, as follows:
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- Phy interrupts
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- Completion queue interrupts
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- Fatal interrupts
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Phy interrupts : Each phy has 3 interrupt sources:
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- broadcast
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- phyup
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- abnormal
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The phy interrupts are ordered into groups of 3 per phy
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(broadcast, phyup, and abnormal) in increasing order.
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Completion queue interrupts : each completion queue has 1
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interrupt source.
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The interrupts are ordered in increasing order.
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Fatal interrupts : the fatal interrupts are ordered as follows:
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- ECC
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- AXI bus
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For v2 hw: Interrupts for phys, Sata, and completion queues;
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the interrupts are ordered in 3 groups, as follows:
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- Phy interrupts
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- Sata interrupts
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- Completion queue interrupts
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Phy interrupts : Each controller has 2 phy interrupts:
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- phy up/down
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- channel interrupt
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Sata interrupts : Each phy on the controller has 1 Sata
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interrupt. The interrupts are ordered in increasing
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order.
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Completion queue interrupts : each completion queue has 1
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interrupt source. The interrupts are ordered in
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increasing order.
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Optional main node properties:
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- hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the
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"am-max-transmissions" limitation.
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Example:
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sas0: sas@c1000000 {
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compatible = "hisilicon,hip05-sas-v1";
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sas-addr = [50 01 88 20 16 00 00 0a];
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reg = <0x0 0xc1000000 0x0 0x10000>;
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hisilicon,sas-syscon = <&pcie_sas>;
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ctrl-reset-reg = <0xa60>;
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ctrl-reset-sts-reg = <0x5a30>;
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ctrl-clock-ena-reg = <0x338>;
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queue-count = <32>;
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phy-count = <8>;
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dma-coherent;
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interrupt-parent = <&mbigen_dsa>;
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interrupts = <259 4>,<263 4>,<264 4>,/* phy0 */
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<269 4>,<273 4>,<274 4>,/* phy1 */
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<279 4>,<283 4>,<284 4>,/* phy2 */
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<289 4>,<293 4>,<294 4>,/* phy3 */
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<299 4>,<303 4>,<304 4>,/* phy4 */
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<309 4>,<313 4>,<314 4>,/* phy5 */
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<319 4>,<323 4>,<324 4>,/* phy6 */
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<329 4>,<333 4>,<334 4>,/* phy7 */
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<336 1>,<337 1>,<338 1>,/* cq0-2 */
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<339 1>,<340 1>,<341 1>,/* cq3-5 */
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<342 1>,<343 1>,<344 1>,/* cq6-8 */
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<345 1>,<346 1>,<347 1>,/* cq9-11 */
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<348 1>,<349 1>,<350 1>,/* cq12-14 */
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<351 1>,<352 1>,<353 1>,/* cq15-17 */
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<354 1>,<355 1>,<356 1>,/* cq18-20 */
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<357 1>,<358 1>,<359 1>,/* cq21-23 */
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<360 1>,<361 1>,<362 1>,/* cq24-26 */
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<363 1>,<364 1>,<365 1>,/* cq27-29 */
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<366 1>,<367 1>/* cq30-31 */
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<376 4>,/* fatal ecc */
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<381 4>;/* fatal axi */
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status = "disabled";
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};
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