127 lines
4.8 KiB
Plaintext
127 lines
4.8 KiB
Plaintext
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CS35L33 Speaker Amplifier
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Required properties:
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- compatible : "cirrus,cs35l33"
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- reg : the I2C address of the device for I2C
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- VA-supply, VP-supply : power supplies for the device,
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as covered in
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Documentation/devicetree/bindings/regulator/regulator.txt.
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Optional properties:
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- reset-gpios : gpio used to reset the amplifier
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- interrupt-parent : Specifies the phandle of the interrupt controller to
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which the IRQs from CS35L33 are delivered to.
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- interrupts : IRQ line info CS35L33.
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(See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
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for further information relating to interrupt properties)
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- cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is
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0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
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a value of 1 and will increase at a step size of 100mV until a maximum of
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8000mV.
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- cirrus,ramp-rate : On power up, it affects the time from when the power
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up sequence begins to the time the audio reaches a full-scale output.
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On power down, it affects the time from when the power-down sequence
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begins to when the amplifier disables the PWM outputs. If this property
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is not set then soft ramping will be disabled and ramp time would be
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20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms,
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60ms,100ms,175ms respectively for 48KHz sample rate.
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- cirrus,boost-ipk : The maximum current allowed for the boost converter.
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The range starts at 1850000uA and goes to a maximum of 3600000uA
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with a step size of 15625uA. The default is 2500000uA.
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- cirrus,imon-adc-scale : Configures the scaling of data bits from the IMON
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ADC data word. This property can be set as a value of 0 for bits 15 down
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to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8.
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Optional H/G Algorithm sub-node:
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The cs35l33 node can have a single "cirrus,hg-algo" sub-node that will enable
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the internal H/G Algorithm.
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- cirrus,hg-algo : Sub-node for internal Class H/G algorithm that
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controls the amplifier supplies.
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Optional properties for the "cirrus,hg-algo" sub-node:
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- cirrus,mem-depth : Memory depth for the Class H/G algorithm measured in
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LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
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depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles.
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cirrus,release-rate : The number of consecutive LRCLK periods before
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allowing release condition tracking updates. The number of LRCLK periods
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start at 3 to a maximum of 255.
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- cirrus,ldo-thld : Configures the signal threshold at which the PWM output
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stage enters LDO operation. Starts as a default value of 50mV for a value
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of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
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0xF).
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- cirrus,ldo-path-disable : This is a boolean property. If present, the H/G
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algorithm uses the max detection path. If not present, the LDO
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detection path is used.
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- cirrus,ldo-entry-delay : The LDO entry delay in milliseconds before the H/G
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algorithm switches to the LDO voltage. This property can be set to values
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from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms.
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The default is 100ms.
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- cirrus,vp-hg-auto : This is a boolean property. When set, class H/G VPhg
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automatic updating is enabled.
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- cirrus,vp-hg : Class H/G algorithm VPhg. Controls the H/G algorithm's
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reference to the VP voltage for when to start generating a boosted VBST.
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The reference voltage starts at 3000mV with a value of 0x3 and is increased
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by 100mV per step to a maximum of 5500mV.
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- cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is
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allowed to increase to a higher voltage when using VPhg automatic
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tracking. This property can be set to values from 0 to 3 with rates of 128
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periods, 2048 periods, 32768 periods, and 524288 periods.
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The default is 32768 periods.
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- cirrus,vp-hg-va : VA calculation reference for automatic VPhg tracking
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using VPMON. This property can be set to values from 0 to 6 starting at
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1800mV with a step size of 50mV up to a maximum value of 1750mV.
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Default is 1800mV.
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Example:
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cs35l33: cs35l33@40 {
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compatible = "cirrus,cs35l33";
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reg = <0x40>;
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VA-supply = <&ldo5_reg>;
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VP-supply = <&ldo5_reg>;
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interrupt-parent = <&gpio8>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&cs47l91 34 0>;
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cirrus,ramp-rate = <0x0>;
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cirrus,boost-ctl = <0x30>; /* VBST = 8000mV */
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cirrus,boost-ipk = <0xE0>; /* 3600mA */
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cirrus,imon-adc-scale = <0> /* Bits 15 down to 0 */
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cirrus,hg-algo {
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cirrus,mem-depth = <0x3>;
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cirrus,release-rate = <0x3>;
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cirrus,ldo-thld = <0x1>;
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cirrus,ldo-path-disable = <0x0>;
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cirrus,ldo-entry-delay=<0x4>;
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cirrus,vp-hg-auto;
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cirrus,vp-hg=<0xF>;
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cirrus,vp-hg-rate=<0x2>;
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cirrus,vp-hg-va=<0x0>;
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};
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};
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