226 lines
8.8 KiB
Plaintext
226 lines
8.8 KiB
Plaintext
|
Tegra124 SOCTHERM thermal management system
|
||
|
|
|
||
|
|
The SOCTHERM IP block contains thermal sensors, support for polled
|
||
|
|
or interrupt-based thermal monitoring, CPU and GPU throttling based
|
||
|
|
on temperature trip points, and handling external overcurrent
|
||
|
|
notifications. It is also used to manage emergency shutdown in an
|
||
|
|
overheating situation.
|
||
|
|
|
||
|
|
Required properties :
|
||
|
|
- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
|
||
|
|
For Tegra132, must contain "nvidia,tegra132-soctherm".
|
||
|
|
For Tegra210, must contain "nvidia,tegra210-soctherm".
|
||
|
|
- reg : Should contain at least 2 entries for each entry in reg-names:
|
||
|
|
- SOCTHERM register set
|
||
|
|
- Tegra CAR register set: Required for Tegra124 and Tegra210.
|
||
|
|
- CCROC register set: Required for Tegra132.
|
||
|
|
- reg-names : Should contain at least 2 entries:
|
||
|
|
- soctherm-reg
|
||
|
|
- car-reg
|
||
|
|
- ccroc-reg
|
||
|
|
- interrupts : Defines the interrupt used by SOCTHERM
|
||
|
|
- clocks : Must contain an entry for each entry in clock-names.
|
||
|
|
See ../clocks/clock-bindings.txt for details.
|
||
|
|
- clock-names : Must include the following entries:
|
||
|
|
- tsensor
|
||
|
|
- soctherm
|
||
|
|
- resets : Must contain an entry for each entry in reset-names.
|
||
|
|
See ../reset/reset.txt for details.
|
||
|
|
- reset-names : Must include the following entries:
|
||
|
|
- soctherm
|
||
|
|
- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description
|
||
|
|
of this property. See <dt-bindings/thermal/tegra124-soctherm.h> for a
|
||
|
|
list of valid values when referring to thermal sensors.
|
||
|
|
- hw-pllx-offsets : All the tsensors can be invalidated under certain conditions
|
||
|
|
and be configured to report temperature as an offset from the PLLX tsensor.
|
||
|
|
When present this property enables this offsetting. It is an array of triplets
|
||
|
|
where each triplet represents a tsensor id followed by a min and a max offset.
|
||
|
|
- All tsensors except the PLLX sensor may have an offset defined and offsets
|
||
|
|
for PLLX tsensor are ignored. The list of valid tsensor ids are present in
|
||
|
|
<dt-bindings/thermal/tegra124-soctherm.h>.
|
||
|
|
- The min and max offsets are used to bound the temperature reported by the
|
||
|
|
soctherm hardware after offsetting has been applied.
|
||
|
|
Offsets are disabled if one or more elements of a triplet are missing or
|
||
|
|
incorrect.
|
||
|
|
- nvidia, thermtrips : When present, this property specifies the temperature at
|
||
|
|
which the soctherm hardware will assert the thermal trigger signal to the
|
||
|
|
Power Management IC, which can be configured to reset or shutdown the device.
|
||
|
|
It is an array of pairs where each pair represents a tsensor id followed by a
|
||
|
|
temperature in milli Celcius. In the absence of this property the critical
|
||
|
|
trip point will be used for thermtrip temperature.
|
||
|
|
- throttle-cfgs: A sub-node which is a container of configuration for each
|
||
|
|
hardware throttle events. These events can be set as cooling devices.
|
||
|
|
* throttle events: Sub-nodes must be named as "light", "heavy", "oc1" - "oc5".
|
||
|
|
Properties:
|
||
|
|
- nvidia,priority: Each throttles has its own throttle settings, so the
|
||
|
|
SW need to set priorities for various throttle, the HW arbiter can select
|
||
|
|
the final throttle settings.
|
||
|
|
Bigger value indicates higher priority, In general, higher priority
|
||
|
|
translates to lower target frequency. SW needs to ensure that critical
|
||
|
|
thermal alarms are given higher priority, and ensure that there is
|
||
|
|
no race if priority of two vectors is set to the same value.
|
||
|
|
The range of this value is 1~100.
|
||
|
|
- nvidia,cpu-throt-percent: This property is for Tegra124 and Tegra210.
|
||
|
|
It is the throttling depth of pulse skippers, it's the percentage
|
||
|
|
throttling.
|
||
|
|
- nvidia,cpu-throt-level: This property is only for Tegra132, it is the
|
||
|
|
level of pulse skippers, which used to throttle clock frequencies. It
|
||
|
|
indicates cpu clock throttling depth, and the depth can be programmed.
|
||
|
|
Must set as following values:
|
||
|
|
TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED
|
||
|
|
TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE
|
||
|
|
- nvidia,gpu-throt-level:This property is for Tegra124 and Tegra210.
|
||
|
|
It is the level of pulse skippers, which used to throttle clock
|
||
|
|
frequencies. It indicates gpu clock throttling depth and can be
|
||
|
|
programmed to any of the following values which represent a throttling
|
||
|
|
percentage:
|
||
|
|
TEGRA_SOCTHERM_THROT_LEVEL_LOW (50%),
|
||
|
|
TEGRA_SOCTHERM_THROT_LEVEL_MED (75%),
|
||
|
|
TEGRA_SOCTHERM_THROT_LEVEL_HIGH (85%),
|
||
|
|
TEGRA_SOCTHERM_THROT_LEVEL_NONE (0%)
|
||
|
|
- #cooling-cells: Should be 1. This cooling device only support on/off state.
|
||
|
|
See ./thermal.txt for a description of this property.
|
||
|
|
Optional properties: The following properties are T210 specific and
|
||
|
|
valid only for OCx throttle events.
|
||
|
|
- nvidia,count-threshold: Specifies the number of OC events that are
|
||
|
|
required for triggering an interrupt. Interrupts are not triggered if
|
||
|
|
the property is missing. A value of 0 will interrupt on every OC alarm.
|
||
|
|
- nvidia,polarity-active-low: Configures the polarity of the OC alaram
|
||
|
|
signal. Accepted values are 1 for assert low and 0 for assert high.
|
||
|
|
Default value is 0.
|
||
|
|
- nvidia,alarm-filter: Number of clocks to filter event. When the filter
|
||
|
|
expires (which means the OC event has not occurred for a long time),
|
||
|
|
the counter is cleared and filter is rearmed. Default value is 0.
|
||
|
|
- nvidia,throttle-period: Specifies the number of uSec for which
|
||
|
|
throttling is engaged after the OC event is deasserted. Default value
|
||
|
|
is 0.
|
||
|
|
|
||
|
|
Note:
|
||
|
|
- the "critical" type trip points will be used to set the temperature at which
|
||
|
|
the SOC_THERM hardware will assert a thermal trigger if the thermtrips property
|
||
|
|
is missing. When the thermtrips property is present the breach of a critical
|
||
|
|
trip point is reported back to the thermal framework.
|
||
|
|
- the "hot" type trip points will be set to SOC_THERM hardware as the throttle
|
||
|
|
temperature. Once the the temperature of this thermal zone is higher
|
||
|
|
than it, it will trigger the HW throttle event.
|
||
|
|
|
||
|
|
Example :
|
||
|
|
|
||
|
|
soctherm@700e2000 {
|
||
|
|
compatible = "nvidia,tegra124-soctherm";
|
||
|
|
reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
|
||
|
|
0x0 0x60006000 0x0 0x400 /* CAR reg_base */
|
||
|
|
reg-names = "soctherm-reg", "car-reg";
|
||
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
|
||
|
|
<&tegra_car TEGRA124_CLK_SOC_THERM>;
|
||
|
|
clock-names = "tsensor", "soctherm";
|
||
|
|
resets = <&tegra_car 78>;
|
||
|
|
reset-names = "soctherm";
|
||
|
|
|
||
|
|
#thermal-sensor-cells = <1>;
|
||
|
|
|
||
|
|
throttle-cfgs {
|
||
|
|
/*
|
||
|
|
* When the "heavy" cooling device triggered,
|
||
|
|
* the HW will skip cpu clock's pulse in 85% depth
|
||
|
|
*/
|
||
|
|
throttle_heavy: heavy {
|
||
|
|
nvidia,priority = <100>;
|
||
|
|
nvidia,cpu-throt-percent = <85>;
|
||
|
|
|
||
|
|
#cooling-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* When the "light" cooling device triggered,
|
||
|
|
* the HW will skip cpu clock's pulse in 50% depth
|
||
|
|
*/
|
||
|
|
throttle_light: light {
|
||
|
|
nvidia,priority = <80>;
|
||
|
|
nvidia,cpu-throt-percent = <50>;
|
||
|
|
|
||
|
|
#cooling-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* If these two devices are triggered in same time, the HW throttle
|
||
|
|
* arbiter will select the highest priority as the final throttle
|
||
|
|
* settings to skip cpu pulse.
|
||
|
|
*/
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
Example: referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" :
|
||
|
|
|
||
|
|
soctherm@700e2000 {
|
||
|
|
compatible = "nvidia,tegra132-soctherm";
|
||
|
|
reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
|
||
|
|
0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
|
||
|
|
reg-names = "soctherm-reg", "ccroc-reg";
|
||
|
|
|
||
|
|
throttle-cfgs {
|
||
|
|
/*
|
||
|
|
* When the "heavy" cooling device triggered,
|
||
|
|
* the HW will skip cpu clock's pulse in HIGH level
|
||
|
|
*/
|
||
|
|
throttle_heavy: heavy {
|
||
|
|
nvidia,priority = <100>;
|
||
|
|
nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
|
||
|
|
|
||
|
|
#cooling-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* When the "light" cooling device triggered,
|
||
|
|
* the HW will skip cpu clock's pulse in MED level
|
||
|
|
*/
|
||
|
|
throttle_light: light {
|
||
|
|
nvidia,priority = <80>;
|
||
|
|
nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
|
||
|
|
|
||
|
|
#cooling-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* If these two devices are triggered in same time, the HW throttle
|
||
|
|
* arbiter will select the highest priority as the final throttle
|
||
|
|
* settings to skip cpu pulse.
|
||
|
|
*/
|
||
|
|
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
Example: referring to thermal sensors :
|
||
|
|
|
||
|
|
thermal-zones {
|
||
|
|
cpu {
|
||
|
|
polling-delay-passive = <1000>;
|
||
|
|
polling-delay = <1000>;
|
||
|
|
|
||
|
|
thermal-sensors =
|
||
|
|
<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
|
||
|
|
|
||
|
|
trips {
|
||
|
|
cpu_shutdown_trip: shutdown-trip {
|
||
|
|
temperature = <102500>;
|
||
|
|
hysteresis = <1000>;
|
||
|
|
type = "critical";
|
||
|
|
};
|
||
|
|
|
||
|
|
cpu_throttle_trip: throttle-trip {
|
||
|
|
temperature = <100000>;
|
||
|
|
hysteresis = <1000>;
|
||
|
|
type = "hot";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
cooling-maps {
|
||
|
|
map0 {
|
||
|
|
trip = <&cpu_throttle_trip>;
|
||
|
|
cooling-device = <&throttle_heavy 1 1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|