94 lines
2.5 KiB
C
94 lines
2.5 KiB
C
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/*
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* Definitions for use with the Alpha wrperfmon PAL call.
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*/
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#ifndef __ALPHA_WRPERFMON_H
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#define __ALPHA_WRPERFMON_H
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/* Following commands are implemented on all CPUs */
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#define PERFMON_CMD_DISABLE 0
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#define PERFMON_CMD_ENABLE 1
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#define PERFMON_CMD_DESIRED_EVENTS 2
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#define PERFMON_CMD_LOGGING_OPTIONS 3
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/* Following commands on EV5/EV56/PCA56 only */
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#define PERFMON_CMD_INT_FREQ 4
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#define PERFMON_CMD_ENABLE_CLEAR 7
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/* Following commands are on EV5 and better CPUs */
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#define PERFMON_CMD_READ 5
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#define PERFMON_CMD_WRITE 6
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/* Following command are on EV6 and better CPUs */
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#define PERFMON_CMD_ENABLE_WRITE 7
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/* Following command are on EV67 and better CPUs */
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#define PERFMON_CMD_I_STAT 8
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#define PERFMON_CMD_PMPC 9
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/* EV5/EV56/PCA56 Counters */
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#define EV5_PCTR_0 (1UL<<0)
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#define EV5_PCTR_1 (1UL<<1)
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#define EV5_PCTR_2 (1UL<<2)
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#define EV5_PCTR_0_COUNT_SHIFT 48
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#define EV5_PCTR_1_COUNT_SHIFT 32
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#define EV5_PCTR_2_COUNT_SHIFT 16
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#define EV5_PCTR_0_COUNT_MASK 0xffffUL
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#define EV5_PCTR_1_COUNT_MASK 0xffffUL
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#define EV5_PCTR_2_COUNT_MASK 0x3fffUL
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/* EV6 Counters */
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#define EV6_PCTR_0 (1UL<<0)
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#define EV6_PCTR_1 (1UL<<1)
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#define EV6_PCTR_0_COUNT_SHIFT 28
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#define EV6_PCTR_1_COUNT_SHIFT 6
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#define EV6_PCTR_0_COUNT_MASK 0xfffffUL
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#define EV6_PCTR_1_COUNT_MASK 0xfffffUL
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/* EV67 (and subsequent) counters */
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#define EV67_PCTR_0 (1UL<<0)
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#define EV67_PCTR_1 (1UL<<1)
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#define EV67_PCTR_0_COUNT_SHIFT 28
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#define EV67_PCTR_1_COUNT_SHIFT 6
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#define EV67_PCTR_0_COUNT_MASK 0xfffffUL
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#define EV67_PCTR_1_COUNT_MASK 0xfffffUL
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/*
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* The Alpha Architecure Handbook, vers. 4 (1998) appears to have a misprint
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* in Table E-23 regarding the bits that set the event PCTR 1 counts.
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* Hopefully what we have here is correct.
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*/
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#define EV6_PCTR_0_EVENT_MASK 0x10UL
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#define EV6_PCTR_1_EVENT_MASK 0x0fUL
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/* EV6 Events */
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#define EV6_PCTR_0_CYCLES (0UL << 4)
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#define EV6_PCTR_0_INSTRUCTIONS (1UL << 4)
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#define EV6_PCTR_1_CYCLES 0
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#define EV6_PCTR_1_BRANCHES 1
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#define EV6_PCTR_1_BRANCH_MISPREDICTS 2
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#define EV6_PCTR_1_DTB_SINGLE_MISSES 3
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#define EV6_PCTR_1_DTB_DOUBLE_MISSES 4
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#define EV6_PCTR_1_ITB_MISSES 5
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#define EV6_PCTR_1_UNALIGNED_TRAPS 6
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#define EV6_PCTR_1_REPLY_TRAPS 7
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/* From the Alpha Architecture Reference Manual, 4th edn., 2002 */
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#define EV67_PCTR_MODE_MASK 0x10UL
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#define EV67_PCTR_EVENT_MASK 0x0CUL
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#define EV67_PCTR_MODE_PROFILEME (1UL<<4)
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#define EV67_PCTR_MODE_AGGREGATE (0UL<<4)
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#define EV67_PCTR_INSTR_CYCLES (0UL<<2)
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#define EV67_PCTR_CYCLES_UNDEF (1UL<<2)
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#define EV67_PCTR_INSTR_BCACHEMISS (2UL<<2)
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#define EV67_PCTR_CYCLES_MBOX (3UL<<2)
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#endif
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