382 lines
9.4 KiB
C
382 lines
9.4 KiB
C
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_ARC_ARCREGS_H
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#define _ASM_ARC_ARCREGS_H
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/* Build Configuration Registers */
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#define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
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#define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
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#define ARC_REG_CRC_BCR 0x62
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#define ARC_REG_VECBASE_BCR 0x68
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#define ARC_REG_PERIBASE_BCR 0x69
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#define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
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#define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
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#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
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#define ARC_REG_SLC_BCR 0xce
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#define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
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#define ARC_REG_TIMERS_BCR 0x75
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#define ARC_REG_AP_BCR 0x76
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#define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
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#define ARC_REG_XY_MEM_BCR 0x79
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#define ARC_REG_MAC_BCR 0x7a
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#define ARC_REG_MUL_BCR 0x7b
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#define ARC_REG_SWAP_BCR 0x7c
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#define ARC_REG_NORM_BCR 0x7d
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#define ARC_REG_MIXMAX_BCR 0x7e
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#define ARC_REG_BARREL_BCR 0x7f
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#define ARC_REG_D_UNCACH_BCR 0x6A
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#define ARC_REG_BPU_BCR 0xc0
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#define ARC_REG_ISA_CFG_BCR 0xc1
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#define ARC_REG_RTT_BCR 0xF2
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#define ARC_REG_IRQ_BCR 0xF3
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#define ARC_REG_SMART_BCR 0xFF
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#define ARC_REG_CLUSTER_BCR 0xcf
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#define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
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/* status32 Bits Positions */
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#define STATUS_AE_BIT 5 /* Exception active */
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#define STATUS_DE_BIT 6 /* PC is in delay slot */
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#define STATUS_U_BIT 7 /* User/Kernel mode */
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#define STATUS_Z_BIT 11
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#define STATUS_L_BIT 12 /* Loop inhibit */
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/* These masks correspond to the status word(STATUS_32) bits */
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#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
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#define STATUS_DE_MASK (1<<STATUS_DE_BIT)
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#define STATUS_U_MASK (1<<STATUS_U_BIT)
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#define STATUS_Z_MASK (1<<STATUS_Z_BIT)
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#define STATUS_L_MASK (1<<STATUS_L_BIT)
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/*
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* ECR: Exception Cause Reg bits-n-pieces
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* [23:16] = Exception Vector
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* [15: 8] = Exception Cause Code
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* [ 7: 0] = Exception Parameters (for certain types only)
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*/
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#ifdef CONFIG_ISA_ARCOMPACT
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#define ECR_V_MEM_ERR 0x01
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#define ECR_V_INSN_ERR 0x02
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#define ECR_V_MACH_CHK 0x20
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#define ECR_V_ITLB_MISS 0x21
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#define ECR_V_DTLB_MISS 0x22
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#define ECR_V_PROTV 0x23
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#define ECR_V_TRAP 0x25
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#else
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#define ECR_V_MEM_ERR 0x01
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#define ECR_V_INSN_ERR 0x02
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#define ECR_V_MACH_CHK 0x03
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#define ECR_V_ITLB_MISS 0x04
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#define ECR_V_DTLB_MISS 0x05
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#define ECR_V_PROTV 0x06
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#define ECR_V_TRAP 0x09
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#endif
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/* DTLB Miss and Protection Violation Cause Codes */
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#define ECR_C_PROTV_INST_FETCH 0x00
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#define ECR_C_PROTV_LOAD 0x01
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#define ECR_C_PROTV_STORE 0x02
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#define ECR_C_PROTV_XCHG 0x03
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#define ECR_C_PROTV_MISALIG_DATA 0x04
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#define ECR_C_BIT_PROTV_MISALIG_DATA 10
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/* Machine Check Cause Code Values */
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#define ECR_C_MCHK_DUP_TLB 0x01
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/* DTLB Miss Exception Cause Code Values */
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#define ECR_C_BIT_DTLB_LD_MISS 8
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#define ECR_C_BIT_DTLB_ST_MISS 9
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/* Auxiliary registers */
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#define AUX_IDENTITY 4
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#define AUX_INTR_VEC_BASE 0x25
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#define AUX_VOL 0x5e
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/*
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* Floating Pt Registers
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* Status regs are read-only (build-time) so need not be saved/restored
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*/
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#define ARC_AUX_FP_STAT 0x300
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#define ARC_AUX_DPFP_1L 0x301
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#define ARC_AUX_DPFP_1H 0x302
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#define ARC_AUX_DPFP_2L 0x303
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#define ARC_AUX_DPFP_2H 0x304
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#define ARC_AUX_DPFP_STAT 0x305
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#ifndef __ASSEMBLY__
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/*
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******************************************************************
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* Inline ASM macros to read/write AUX Regs
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* Essentially invocation of lr/sr insns from "C"
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*/
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#if 1
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#define read_aux_reg(reg) __builtin_arc_lr(reg)
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/* gcc builtin sr needs reg param to be long immediate */
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#define write_aux_reg(reg_immed, val) \
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__builtin_arc_sr((unsigned int)(val), reg_immed)
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#else
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#define read_aux_reg(reg) \
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({ \
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unsigned int __ret; \
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__asm__ __volatile__( \
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" lr %0, [%1]" \
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: "=r"(__ret) \
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: "i"(reg)); \
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__ret; \
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})
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/*
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* Aux Reg address is specified as long immediate by caller
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* e.g.
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* write_aux_reg(0x69, some_val);
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* This generates tightest code.
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*/
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#define write_aux_reg(reg_imm, val) \
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({ \
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__asm__ __volatile__( \
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" sr %0, [%1] \n" \
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: \
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: "ir"(val), "i"(reg_imm)); \
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})
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/*
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* Aux Reg address is specified in a variable
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* * e.g.
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* reg_num = 0x69
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* write_aux_reg2(reg_num, some_val);
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* This has to generate glue code to load the reg num from
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* memory to a reg hence not recommended.
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*/
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#define write_aux_reg2(reg_in_var, val) \
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({ \
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unsigned int tmp; \
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\
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__asm__ __volatile__( \
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" ld %0, [%2] \n\t" \
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" sr %1, [%0] \n\t" \
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: "=&r"(tmp) \
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: "r"(val), "memory"(®_in_var)); \
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})
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#endif
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#define READ_BCR(reg, into) \
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{ \
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unsigned int tmp; \
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tmp = read_aux_reg(reg); \
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if (sizeof(tmp) == sizeof(into)) { \
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into = *((typeof(into) *)&tmp); \
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} else { \
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extern void bogus_undefined(void); \
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bogus_undefined(); \
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} \
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}
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#define WRITE_AUX(reg, into) \
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{ \
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unsigned int tmp; \
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if (sizeof(tmp) == sizeof(into)) { \
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tmp = (*(unsigned int *)&(into)); \
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write_aux_reg(reg, tmp); \
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} else { \
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extern void bogus_undefined(void); \
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bogus_undefined(); \
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} \
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}
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/* Helpers */
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#define TO_KB(bytes) ((bytes) >> 10)
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#define TO_MB(bytes) (TO_KB(bytes) >> 10)
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#define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
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#define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
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/*
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***************************************************************
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* Build Configuration Registers, with encoded hardware config
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*/
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struct bcr_identity {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int chip_id:16, cpu_id:8, family:8;
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#else
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unsigned int family:8, cpu_id:8, chip_id:16;
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#endif
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};
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struct bcr_isa {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
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pad1:11, atomic1:1, ver:8;
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#else
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unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
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ldd:1, pad2:4, div_rem:4;
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#endif
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};
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struct bcr_mpy {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
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#else
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unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
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#endif
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};
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struct bcr_extn_xymem {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
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#else
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unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
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#endif
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};
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struct bcr_iccm_arcompact {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int base:16, pad:5, sz:3, ver:8;
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#else
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unsigned int ver:8, sz:3, pad:5, base:16;
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#endif
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};
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struct bcr_iccm_arcv2 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
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#else
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unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
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#endif
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};
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struct bcr_dccm_arcompact {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int res:21, sz:3, ver:8;
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#else
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unsigned int ver:8, sz:3, res:21;
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#endif
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};
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struct bcr_dccm_arcv2 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
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#else
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unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
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#endif
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};
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/* ARCompact: Both SP and DP FPU BCRs have same format */
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struct bcr_fp_arcompact {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int fast:1, ver:8;
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#else
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unsigned int ver:8, fast:1;
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#endif
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};
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struct bcr_fp_arcv2 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
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#else
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unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
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#endif
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};
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struct bcr_timer {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
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#else
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unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
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#endif
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};
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struct bcr_bpu_arcompact {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
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#else
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unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
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#endif
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};
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struct bcr_bpu_arcv2 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
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#else
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unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
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#endif
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};
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struct bcr_generic {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int info:24, ver:8;
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#else
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unsigned int ver:8, info:24;
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#endif
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};
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/*
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*******************************************************************
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* Generic structures to hold build configuration used at runtime
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*/
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struct cpuinfo_arc_mmu {
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unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
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unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
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};
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struct cpuinfo_arc_cache {
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unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1;
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};
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struct cpuinfo_arc_bpu {
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unsigned int ver, full, num_cache, num_pred;
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};
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struct cpuinfo_arc_ccm {
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unsigned int base_addr, sz;
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};
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struct cpuinfo_arc {
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struct cpuinfo_arc_cache icache, dcache, slc;
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struct cpuinfo_arc_mmu mmu;
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struct cpuinfo_arc_bpu bpu;
|
||
|
|
struct bcr_identity core;
|
||
|
|
struct bcr_isa isa;
|
||
|
|
const char *details, *name;
|
||
|
|
unsigned int vec_base;
|
||
|
|
struct cpuinfo_arc_ccm iccm, dccm;
|
||
|
|
struct {
|
||
|
|
unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
|
||
|
|
fpu_sp:1, fpu_dp:1, pad2:6,
|
||
|
|
debug:1, ap:1, smart:1, rtt:1, pad3:4,
|
||
|
|
timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
|
||
|
|
} extn;
|
||
|
|
struct bcr_mpy extn_mpy;
|
||
|
|
struct bcr_extn_xymem extn_xymem;
|
||
|
|
};
|
||
|
|
|
||
|
|
extern struct cpuinfo_arc cpuinfo_arc700[];
|
||
|
|
|
||
|
|
static inline int is_isa_arcv2(void)
|
||
|
|
{
|
||
|
|
return IS_ENABLED(CONFIG_ISA_ARCV2);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int is_isa_arcompact(void)
|
||
|
|
{
|
||
|
|
return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* __ASEMBLY__ */
|
||
|
|
|
||
|
|
#endif /* _ASM_ARC_ARCREGS_H */
|