613 lines
15 KiB
C
613 lines
15 KiB
C
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_ARC_ATOMIC_H
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#define _ASM_ARC_ATOMIC_H
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/compiler.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#include <asm/smp.h>
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#define ATOMIC_INIT(i) { (i) }
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#ifndef CONFIG_ARC_PLAT_EZNPS
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#define atomic_read(v) READ_ONCE((v)->counter)
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#ifdef CONFIG_ARC_HAS_LLSC
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#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned int val; \
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\
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__asm__ __volatile__( \
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"1: llock %[val], [%[ctr]] \n" \
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" " #asm_op " %[val], %[val], %[i] \n" \
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" scond %[val], [%[ctr]] \n" \
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" bnz 1b \n" \
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: [val] "=&r" (val) /* Early clobber to prevent reg reuse */ \
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: [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \
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[i] "ir" (i) \
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: "cc"); \
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} \
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned int val; \
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\
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/* \
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* Explicit full memory barrier needed before/after as \
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* LLOCK/SCOND thmeselves don't provide any such semantics \
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*/ \
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smp_mb(); \
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\
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__asm__ __volatile__( \
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"1: llock %[val], [%[ctr]] \n" \
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" " #asm_op " %[val], %[val], %[i] \n" \
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" scond %[val], [%[ctr]] \n" \
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" bnz 1b \n" \
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: [val] "=&r" (val) \
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: [ctr] "r" (&v->counter), \
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[i] "ir" (i) \
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: "cc"); \
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\
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smp_mb(); \
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\
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return val; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static inline int atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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unsigned int val, orig; \
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\
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/* \
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* Explicit full memory barrier needed before/after as \
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* LLOCK/SCOND thmeselves don't provide any such semantics \
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*/ \
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smp_mb(); \
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\
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__asm__ __volatile__( \
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"1: llock %[orig], [%[ctr]] \n" \
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" " #asm_op " %[val], %[orig], %[i] \n" \
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" scond %[val], [%[ctr]] \n" \
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" bnz 1b \n" \
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: [val] "=&r" (val), \
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[orig] "=&r" (orig) \
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: [ctr] "r" (&v->counter), \
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[i] "ir" (i) \
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: "cc"); \
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\
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smp_mb(); \
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\
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return orig; \
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}
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#else /* !CONFIG_ARC_HAS_LLSC */
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#ifndef CONFIG_SMP
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/* violating atomic_xxx API locking protocol in UP for optimization sake */
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#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
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#else
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static inline void atomic_set(atomic_t *v, int i)
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{
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/*
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* Independent of hardware support, all of the atomic_xxx() APIs need
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* to follow the same locking rules to make sure that a "hardware"
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* atomic insn (e.g. LD) doesn't clobber an "emulated" atomic insn
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* sequence
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*
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* Thus atomic_set() despite being 1 insn (and seemingly atomic)
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* requires the locking.
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*/
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unsigned long flags;
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atomic_ops_lock(flags);
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WRITE_ONCE(v->counter, i);
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atomic_ops_unlock(flags);
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}
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#endif
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/*
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* Non hardware assisted Atomic-R-M-W
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* Locking would change to irq-disabling only (UP) and spinlocks (SMP)
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*/
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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\
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atomic_ops_lock(flags); \
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v->counter c_op i; \
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atomic_ops_unlock(flags); \
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}
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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unsigned long temp; \
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\
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/* \
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* spin lock/unlock provides the needed smp_mb() before/after \
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*/ \
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atomic_ops_lock(flags); \
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temp = v->counter; \
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temp c_op i; \
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v->counter = temp; \
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atomic_ops_unlock(flags); \
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\
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return temp; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static inline int atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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unsigned long orig; \
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\
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/* \
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* spin lock/unlock provides the needed smp_mb() before/after \
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*/ \
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atomic_ops_lock(flags); \
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orig = v->counter; \
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v->counter c_op i; \
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atomic_ops_unlock(flags); \
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\
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return orig; \
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}
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#endif /* !CONFIG_ARC_HAS_LLSC */
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_OP_RETURN(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(add, +=, add)
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ATOMIC_OPS(sub, -=, sub)
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#define atomic_andnot atomic_andnot
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(and, &=, and)
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ATOMIC_OPS(andnot, &= ~, bic)
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ATOMIC_OPS(or, |=, or)
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ATOMIC_OPS(xor, ^=, xor)
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#else /* CONFIG_ARC_PLAT_EZNPS */
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static inline int atomic_read(const atomic_t *v)
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{
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int temp;
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__asm__ __volatile__(
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" ld.di %0, [%1]"
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: "=r"(temp)
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: "r"(&v->counter)
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: "memory");
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return temp;
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}
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static inline void atomic_set(atomic_t *v, int i)
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{
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__asm__ __volatile__(
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" st.di %0,[%1]"
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:
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: "r"(i), "r"(&v->counter)
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: "memory");
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}
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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__asm__ __volatile__( \
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" mov r2, %0\n" \
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" mov r3, %1\n" \
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" .word %2\n" \
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: \
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: "r"(i), "r"(&v->counter), "i"(asm_op) \
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: "r2", "r3", "memory"); \
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} \
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned int temp = i; \
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\
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/* Explicit full memory barrier needed before/after */ \
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smp_mb(); \
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\
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__asm__ __volatile__( \
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" mov r2, %0\n" \
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" mov r3, %1\n" \
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" .word %2\n" \
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" mov %0, r2" \
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: "+r"(temp) \
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: "r"(&v->counter), "i"(asm_op) \
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: "r2", "r3", "memory"); \
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\
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smp_mb(); \
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\
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temp c_op i; \
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\
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return temp; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static inline int atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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unsigned int temp = i; \
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\
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/* Explicit full memory barrier needed before/after */ \
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smp_mb(); \
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\
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__asm__ __volatile__( \
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" mov r2, %0\n" \
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" mov r3, %1\n" \
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" .word %2\n" \
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" mov %0, r2" \
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: "+r"(temp) \
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: "r"(&v->counter), "i"(asm_op) \
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: "r2", "r3", "memory"); \
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\
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smp_mb(); \
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\
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return temp; \
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}
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_OP_RETURN(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3)
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#define atomic_sub(i, v) atomic_add(-(i), (v))
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#define atomic_sub_return(i, v) atomic_add_return(-(i), (v))
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#define atomic_fetch_sub(i, v) atomic_fetch_add(-(i), (v))
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(and, &=, CTOP_INST_AAND_DI_R2_R2_R3)
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#define atomic_andnot(mask, v) atomic_and(~(mask), (v))
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#define atomic_fetch_andnot(mask, v) atomic_fetch_and(~(mask), (v))
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ATOMIC_OPS(or, |=, CTOP_INST_AOR_DI_R2_R2_R3)
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ATOMIC_OPS(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
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#endif /* CONFIG_ARC_PLAT_EZNPS */
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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/**
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* __atomic_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns the old value of @v
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*/
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#define __atomic_add_unless(v, a, u) \
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({ \
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int c, old; \
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\
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/* \
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* Explicit full memory barrier needed before/after as \
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* LLOCK/SCOND thmeselves don't provide any such semantics \
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*/ \
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smp_mb(); \
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\
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c = atomic_read(v); \
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while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c)\
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c = old; \
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\
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smp_mb(); \
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\
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c; \
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})
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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#define atomic_inc(v) atomic_add(1, v)
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#define atomic_dec(v) atomic_sub(1, v)
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#define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
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#define atomic_inc_return(v) atomic_add_return(1, (v))
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#define atomic_dec_return(v) atomic_sub_return(1, (v))
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#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
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#define atomic_add_negative(i, v) (atomic_add_return(i, v) < 0)
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#ifdef CONFIG_GENERIC_ATOMIC64
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#include <asm-generic/atomic64.h>
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#else /* Kconfig ensures this is only enabled with needed h/w assist */
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/*
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* ARCv2 supports 64-bit exclusive load (LLOCKD) / store (SCONDD)
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* - The address HAS to be 64-bit aligned
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* - There are 2 semantics involved here:
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* = exclusive implies no interim update between load/store to same addr
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* = both words are observed/updated together: this is guaranteed even
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* for regular 64-bit load (LDD) / store (STD). Thus atomic64_set()
|
||
|
|
* is NOT required to use LLOCKD+SCONDD, STD suffices
|
||
|
|
*/
|
||
|
|
|
||
|
|
typedef struct {
|
||
|
|
aligned_u64 counter;
|
||
|
|
} atomic64_t;
|
||
|
|
|
||
|
|
#define ATOMIC64_INIT(a) { (a) }
|
||
|
|
|
||
|
|
static inline long long atomic64_read(const atomic64_t *v)
|
||
|
|
{
|
||
|
|
unsigned long long val;
|
||
|
|
|
||
|
|
__asm__ __volatile__(
|
||
|
|
" ldd %0, [%1] \n"
|
||
|
|
: "=r"(val)
|
||
|
|
: "r"(&v->counter));
|
||
|
|
|
||
|
|
return val;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void atomic64_set(atomic64_t *v, long long a)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* This could have been a simple assignment in "C" but would need
|
||
|
|
* explicit volatile. Otherwise gcc optimizers could elide the store
|
||
|
|
* which borked atomic64 self-test
|
||
|
|
* In the inline asm version, memory clobber needed for exact same
|
||
|
|
* reason, to tell gcc about the store.
|
||
|
|
*
|
||
|
|
* This however is not needed for sibling atomic64_add() etc since both
|
||
|
|
* load/store are explicitly done in inline asm. As long as API is used
|
||
|
|
* for each access, gcc has no way to optimize away any load/store
|
||
|
|
*/
|
||
|
|
__asm__ __volatile__(
|
||
|
|
" std %0, [%1] \n"
|
||
|
|
:
|
||
|
|
: "r"(a), "r"(&v->counter)
|
||
|
|
: "memory");
|
||
|
|
}
|
||
|
|
|
||
|
|
#define ATOMIC64_OP(op, op1, op2) \
|
||
|
|
static inline void atomic64_##op(long long a, atomic64_t *v) \
|
||
|
|
{ \
|
||
|
|
unsigned long long val; \
|
||
|
|
\
|
||
|
|
__asm__ __volatile__( \
|
||
|
|
"1: \n" \
|
||
|
|
" llockd %0, [%1] \n" \
|
||
|
|
" " #op1 " %L0, %L0, %L2 \n" \
|
||
|
|
" " #op2 " %H0, %H0, %H2 \n" \
|
||
|
|
" scondd %0, [%1] \n" \
|
||
|
|
" bnz 1b \n" \
|
||
|
|
: "=&r"(val) \
|
||
|
|
: "r"(&v->counter), "ir"(a) \
|
||
|
|
: "cc"); \
|
||
|
|
} \
|
||
|
|
|
||
|
|
#define ATOMIC64_OP_RETURN(op, op1, op2) \
|
||
|
|
static inline long long atomic64_##op##_return(long long a, atomic64_t *v) \
|
||
|
|
{ \
|
||
|
|
unsigned long long val; \
|
||
|
|
\
|
||
|
|
smp_mb(); \
|
||
|
|
\
|
||
|
|
__asm__ __volatile__( \
|
||
|
|
"1: \n" \
|
||
|
|
" llockd %0, [%1] \n" \
|
||
|
|
" " #op1 " %L0, %L0, %L2 \n" \
|
||
|
|
" " #op2 " %H0, %H0, %H2 \n" \
|
||
|
|
" scondd %0, [%1] \n" \
|
||
|
|
" bnz 1b \n" \
|
||
|
|
: [val] "=&r"(val) \
|
||
|
|
: "r"(&v->counter), "ir"(a) \
|
||
|
|
: "cc"); /* memory clobber comes from smp_mb() */ \
|
||
|
|
\
|
||
|
|
smp_mb(); \
|
||
|
|
\
|
||
|
|
return val; \
|
||
|
|
}
|
||
|
|
|
||
|
|
#define ATOMIC64_FETCH_OP(op, op1, op2) \
|
||
|
|
static inline long long atomic64_fetch_##op(long long a, atomic64_t *v) \
|
||
|
|
{ \
|
||
|
|
unsigned long long val, orig; \
|
||
|
|
\
|
||
|
|
smp_mb(); \
|
||
|
|
\
|
||
|
|
__asm__ __volatile__( \
|
||
|
|
"1: \n" \
|
||
|
|
" llockd %0, [%2] \n" \
|
||
|
|
" " #op1 " %L1, %L0, %L3 \n" \
|
||
|
|
" " #op2 " %H1, %H0, %H3 \n" \
|
||
|
|
" scondd %1, [%2] \n" \
|
||
|
|
" bnz 1b \n" \
|
||
|
|
: "=&r"(orig), "=&r"(val) \
|
||
|
|
: "r"(&v->counter), "ir"(a) \
|
||
|
|
: "cc"); /* memory clobber comes from smp_mb() */ \
|
||
|
|
\
|
||
|
|
smp_mb(); \
|
||
|
|
\
|
||
|
|
return orig; \
|
||
|
|
}
|
||
|
|
|
||
|
|
#define ATOMIC64_OPS(op, op1, op2) \
|
||
|
|
ATOMIC64_OP(op, op1, op2) \
|
||
|
|
ATOMIC64_OP_RETURN(op, op1, op2) \
|
||
|
|
ATOMIC64_FETCH_OP(op, op1, op2)
|
||
|
|
|
||
|
|
#define atomic64_andnot atomic64_andnot
|
||
|
|
|
||
|
|
ATOMIC64_OPS(add, add.f, adc)
|
||
|
|
ATOMIC64_OPS(sub, sub.f, sbc)
|
||
|
|
ATOMIC64_OPS(and, and, and)
|
||
|
|
ATOMIC64_OPS(andnot, bic, bic)
|
||
|
|
ATOMIC64_OPS(or, or, or)
|
||
|
|
ATOMIC64_OPS(xor, xor, xor)
|
||
|
|
|
||
|
|
#undef ATOMIC64_OPS
|
||
|
|
#undef ATOMIC64_FETCH_OP
|
||
|
|
#undef ATOMIC64_OP_RETURN
|
||
|
|
#undef ATOMIC64_OP
|
||
|
|
|
||
|
|
static inline long long
|
||
|
|
atomic64_cmpxchg(atomic64_t *ptr, long long expected, long long new)
|
||
|
|
{
|
||
|
|
long long prev;
|
||
|
|
|
||
|
|
smp_mb();
|
||
|
|
|
||
|
|
__asm__ __volatile__(
|
||
|
|
"1: llockd %0, [%1] \n"
|
||
|
|
" brne %L0, %L2, 2f \n"
|
||
|
|
" brne %H0, %H2, 2f \n"
|
||
|
|
" scondd %3, [%1] \n"
|
||
|
|
" bnz 1b \n"
|
||
|
|
"2: \n"
|
||
|
|
: "=&r"(prev)
|
||
|
|
: "r"(ptr), "ir"(expected), "r"(new)
|
||
|
|
: "cc"); /* memory clobber comes from smp_mb() */
|
||
|
|
|
||
|
|
smp_mb();
|
||
|
|
|
||
|
|
return prev;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline long long atomic64_xchg(atomic64_t *ptr, long long new)
|
||
|
|
{
|
||
|
|
long long prev;
|
||
|
|
|
||
|
|
smp_mb();
|
||
|
|
|
||
|
|
__asm__ __volatile__(
|
||
|
|
"1: llockd %0, [%1] \n"
|
||
|
|
" scondd %2, [%1] \n"
|
||
|
|
" bnz 1b \n"
|
||
|
|
"2: \n"
|
||
|
|
: "=&r"(prev)
|
||
|
|
: "r"(ptr), "r"(new)
|
||
|
|
: "cc"); /* memory clobber comes from smp_mb() */
|
||
|
|
|
||
|
|
smp_mb();
|
||
|
|
|
||
|
|
return prev;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* atomic64_dec_if_positive - decrement by 1 if old value positive
|
||
|
|
* @v: pointer of type atomic64_t
|
||
|
|
*
|
||
|
|
* The function returns the old value of *v minus 1, even if
|
||
|
|
* the atomic variable, v, was not decremented.
|
||
|
|
*/
|
||
|
|
|
||
|
|
static inline long long atomic64_dec_if_positive(atomic64_t *v)
|
||
|
|
{
|
||
|
|
long long val;
|
||
|
|
|
||
|
|
smp_mb();
|
||
|
|
|
||
|
|
__asm__ __volatile__(
|
||
|
|
"1: llockd %0, [%1] \n"
|
||
|
|
" sub.f %L0, %L0, 1 # w0 - 1, set C on borrow\n"
|
||
|
|
" sub.c %H0, %H0, 1 # if C set, w1 - 1\n"
|
||
|
|
" brlt %H0, 0, 2f \n"
|
||
|
|
" scondd %0, [%1] \n"
|
||
|
|
" bnz 1b \n"
|
||
|
|
"2: \n"
|
||
|
|
: "=&r"(val)
|
||
|
|
: "r"(&v->counter)
|
||
|
|
: "cc"); /* memory clobber comes from smp_mb() */
|
||
|
|
|
||
|
|
smp_mb();
|
||
|
|
|
||
|
|
return val;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* atomic64_add_unless - add unless the number is a given value
|
||
|
|
* @v: pointer of type atomic64_t
|
||
|
|
* @a: the amount to add to v...
|
||
|
|
* @u: ...unless v is equal to u.
|
||
|
|
*
|
||
|
|
* if (v != u) { v += a; ret = 1} else {ret = 0}
|
||
|
|
* Returns 1 iff @v was not @u (i.e. if add actually happened)
|
||
|
|
*/
|
||
|
|
static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
|
||
|
|
{
|
||
|
|
long long val;
|
||
|
|
int op_done;
|
||
|
|
|
||
|
|
smp_mb();
|
||
|
|
|
||
|
|
__asm__ __volatile__(
|
||
|
|
"1: llockd %0, [%2] \n"
|
||
|
|
" mov %1, 1 \n"
|
||
|
|
" brne %L0, %L4, 2f # continue to add since v != u \n"
|
||
|
|
" breq.d %H0, %H4, 3f # return since v == u \n"
|
||
|
|
" mov %1, 0 \n"
|
||
|
|
"2: \n"
|
||
|
|
" add.f %L0, %L0, %L3 \n"
|
||
|
|
" adc %H0, %H0, %H3 \n"
|
||
|
|
" scondd %0, [%2] \n"
|
||
|
|
" bnz 1b \n"
|
||
|
|
"3: \n"
|
||
|
|
: "=&r"(val), "=&r" (op_done)
|
||
|
|
: "r"(&v->counter), "r"(a), "r"(u)
|
||
|
|
: "cc"); /* memory clobber comes from smp_mb() */
|
||
|
|
|
||
|
|
smp_mb();
|
||
|
|
|
||
|
|
return op_done;
|
||
|
|
}
|
||
|
|
|
||
|
|
#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
|
||
|
|
#define atomic64_inc(v) atomic64_add(1LL, (v))
|
||
|
|
#define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
|
||
|
|
#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
|
||
|
|
#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
|
||
|
|
#define atomic64_dec(v) atomic64_sub(1LL, (v))
|
||
|
|
#define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
|
||
|
|
#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
|
||
|
|
#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
|
||
|
|
|
||
|
|
#endif /* !CONFIG_GENERIC_ATOMIC64 */
|
||
|
|
|
||
|
|
#endif /* !__ASSEMBLY__ */
|
||
|
|
|
||
|
|
#endif
|