231 lines
6.3 KiB
C
231 lines
6.3 KiB
C
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* DMA Coherent API Notes
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*
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* I/O is inherently non-coherent on ARC. So a coherent DMA buffer is
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* implemented by accessing it using a kernel virtual address, with
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* Cache bit off in the TLB entry.
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*
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* The default DMA address == Phy address which is 0x8000_0000 based.
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*/
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#include <linux/dma-mapping.h>
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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static void *arc_dma_alloc(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
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{
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unsigned long order = get_order(size);
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struct page *page;
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phys_addr_t paddr;
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void *kvaddr;
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int need_coh = 1, need_kvaddr = 0;
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page = alloc_pages(gfp, order);
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if (!page)
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return NULL;
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/*
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* IOC relies on all data (even coherent DMA data) being in cache
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* Thus allocate normal cached memory
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*
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* The gains with IOC are two pronged:
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* -For streaming data, elides need for cache maintenance, saving
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* cycles in flush code, and bus bandwidth as all the lines of a
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* buffer need to be flushed out to memory
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* -For coherent data, Read/Write to buffers terminate early in cache
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* (vs. always going to memory - thus are faster)
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*/
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if ((is_isa_arcv2() && ioc_enable) ||
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(attrs & DMA_ATTR_NON_CONSISTENT))
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need_coh = 0;
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/*
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* - A coherent buffer needs MMU mapping to enforce non-cachability
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* - A highmem page needs a virtual handle (hence MMU mapping)
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* independent of cachability
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*/
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if (PageHighMem(page) || need_coh)
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need_kvaddr = 1;
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/* This is linear addr (0x8000_0000 based) */
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paddr = page_to_phys(page);
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*dma_handle = plat_phys_to_dma(dev, paddr);
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/* This is kernel Virtual address (0x7000_0000 based) */
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if (need_kvaddr) {
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kvaddr = ioremap_nocache(paddr, size);
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if (kvaddr == NULL) {
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__free_pages(page, order);
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return NULL;
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}
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} else {
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kvaddr = (void *)(u32)paddr;
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}
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/*
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* Evict any existing L1 and/or L2 lines for the backing page
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* in case it was used earlier as a normal "cached" page.
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* Yeah this bit us - STAR 9000898266
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*
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* Although core does call flush_cache_vmap(), it gets kvaddr hence
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* can't be used to efficiently flush L1 and/or L2 which need paddr
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* Currently flush_cache_vmap nukes the L1 cache completely which
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* will be optimized as a separate commit
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*/
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if (need_coh)
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dma_cache_wback_inv(paddr, size);
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return kvaddr;
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}
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static void arc_dma_free(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle, unsigned long attrs)
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{
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phys_addr_t paddr = plat_dma_to_phys(dev, dma_handle);
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struct page *page = virt_to_page(paddr);
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int is_non_coh = 1;
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is_non_coh = (attrs & DMA_ATTR_NON_CONSISTENT) ||
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(is_isa_arcv2() && ioc_enable);
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if (PageHighMem(page) || !is_non_coh)
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iounmap((void __force __iomem *)vaddr);
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__free_pages(page, get_order(size));
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}
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static int arc_dma_mmap(struct device *dev, struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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unsigned long attrs)
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{
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unsigned long user_count = vma_pages(vma);
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unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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unsigned long pfn = __phys_to_pfn(plat_dma_to_phys(dev, dma_addr));
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unsigned long off = vma->vm_pgoff;
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int ret = -ENXIO;
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
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if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
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return ret;
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if (off < count && user_count <= (count - off)) {
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ret = remap_pfn_range(vma, vma->vm_start,
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pfn + off,
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user_count << PAGE_SHIFT,
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vma->vm_page_prot);
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}
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return ret;
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}
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/*
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* streaming DMA Mapping API...
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* CPU accesses page via normal paddr, thus needs to explicitly made
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* consistent before each use
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*/
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static void _dma_cache_sync(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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switch (dir) {
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case DMA_FROM_DEVICE:
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dma_cache_inv(paddr, size);
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break;
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case DMA_TO_DEVICE:
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dma_cache_wback(paddr, size);
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break;
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case DMA_BIDIRECTIONAL:
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dma_cache_wback_inv(paddr, size);
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break;
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default:
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pr_err("Invalid DMA dir [%d] for OP @ %pa[p]\n", dir, &paddr);
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}
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}
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static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size, enum dma_data_direction dir,
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unsigned long attrs)
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{
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phys_addr_t paddr = page_to_phys(page) + offset;
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_dma_cache_sync(paddr, size, dir);
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return plat_phys_to_dma(dev, paddr);
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}
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static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction dir, unsigned long attrs)
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{
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struct scatterlist *s;
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int i;
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for_each_sg(sg, s, nents, i)
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s->dma_address = dma_map_page(dev, sg_page(s), s->offset,
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s->length, dir);
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return nents;
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}
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static void arc_dma_sync_single_for_cpu(struct device *dev,
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dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
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{
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_dma_cache_sync(plat_dma_to_phys(dev, dma_handle), size, DMA_FROM_DEVICE);
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}
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static void arc_dma_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
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{
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_dma_cache_sync(plat_dma_to_phys(dev, dma_handle), size, DMA_TO_DEVICE);
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}
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static void arc_dma_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sglist, int nelems,
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enum dma_data_direction dir)
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{
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int i;
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struct scatterlist *sg;
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for_each_sg(sglist, sg, nelems, i)
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_dma_cache_sync(sg_phys(sg), sg->length, dir);
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}
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static void arc_dma_sync_sg_for_device(struct device *dev,
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struct scatterlist *sglist, int nelems,
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enum dma_data_direction dir)
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{
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int i;
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struct scatterlist *sg;
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for_each_sg(sglist, sg, nelems, i)
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_dma_cache_sync(sg_phys(sg), sg->length, dir);
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}
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static int arc_dma_supported(struct device *dev, u64 dma_mask)
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{
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/* Support 32 bit DMA mask exclusively */
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return dma_mask == DMA_BIT_MASK(32);
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}
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struct dma_map_ops arc_dma_ops = {
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.alloc = arc_dma_alloc,
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.free = arc_dma_free,
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.mmap = arc_dma_mmap,
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.map_page = arc_dma_map_page,
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.map_sg = arc_dma_map_sg,
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.sync_single_for_device = arc_dma_sync_single_for_device,
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.sync_single_for_cpu = arc_dma_sync_single_for_cpu,
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.sync_sg_for_cpu = arc_dma_sync_sg_for_cpu,
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.sync_sg_for_device = arc_dma_sync_sg_for_device,
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.dma_supported = arc_dma_supported,
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};
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EXPORT_SYMBOL(arc_dma_ops);
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