542 lines
13 KiB
Plaintext
542 lines
13 KiB
Plaintext
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/*
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* Copyright 2016 Linaro Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "arm,realview-pbx";
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chosen { };
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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i2c0 = &i2c;
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};
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memory {
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/* 128 MiB memory @ 0x0 */
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reg = <0x00000000 0x08000000>;
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};
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/* The voltage to the MMC card is hardwired at 3.3V */
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vmmc: regulator-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "vmmc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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veth: regulator-veth {
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compatible = "regulator-fixed";
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regulator-name = "veth";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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xtal24mhz: xtal24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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refclk32khz: refclk32khz {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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timclk: timclk@1M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <24>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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mclk: mclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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kmiclk: kmiclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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sspclk: sspclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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uartclk: uartclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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wdogclk: wdogclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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/* FIXME: this actually hangs off the PLL clocks */
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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flash0@40000000 {
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/* 2 * 32MiB NOR Flash memory */
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compatible = "arm,versatile-flash", "cfi-flash";
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reg = <0x40000000 0x04000000>;
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bank-width = <4>;
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};
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flash1@44000000 {
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/* 2 * 32MiB NOR Flash memory */
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compatible = "arm,versatile-flash", "cfi-flash";
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reg = <0x44000000 0x04000000>;
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bank-width = <4>;
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};
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/* SMSC 9118 ethernet with PHY and EEPROM */
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ethernet: ethernet@4e000000 {
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compatible = "smsc,lan9118", "smsc,lan9115";
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reg = <0x4e000000 0x10000>;
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phy-mode = "mii";
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reg-io-width = <4>;
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smsc,irq-active-high;
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smsc,irq-push-pull;
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vdd33a-supply = <&veth>;
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vddvario-supply = <&veth>;
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};
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usb: usb@4f000000 {
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compatible = "nxp,usb-isp1761";
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reg = <0x4f000000 0x20000>;
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port1-otg;
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};
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soc: soc@0 {
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compatible = "arm,realview-pbx-soc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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regmap = <&syscon>;
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ranges;
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syscon: syscon@10000000 {
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compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
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reg = <0x10000000 0x1000>;
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led@08.0 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x01>;
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label = "versatile:0";
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linux,default-trigger = "heartbeat";
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default-state = "on";
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};
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led@08.1 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x02>;
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label = "versatile:1";
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linux,default-trigger = "mmc0";
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default-state = "off";
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};
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led@08.2 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x04>;
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label = "versatile:2";
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linux,default-trigger = "cpu0";
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default-state = "off";
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};
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led@08.3 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x08>;
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label = "versatile:3";
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default-state = "off";
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};
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led@08.4 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x10>;
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label = "versatile:4";
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default-state = "off";
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};
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led@08.5 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x20>;
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label = "versatile:5";
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default-state = "off";
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};
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led@08.6 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x40>;
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label = "versatile:6";
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default-state = "off";
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};
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led@08.7 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x80>;
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label = "versatile:7";
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default-state = "off";
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};
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oscclk0: osc0@0c {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x0C>;
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clocks = <&xtal24mhz>;
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};
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oscclk1: osc1@10 {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x10>;
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clocks = <&xtal24mhz>;
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};
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oscclk2: osc2@14 {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x14>;
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clocks = <&xtal24mhz>;
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};
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oscclk3: osc3@18 {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x18>;
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clocks = <&xtal24mhz>;
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};
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oscclk4: osc4@1c {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x1c>;
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clocks = <&xtal24mhz>;
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};
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};
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sp810_syscon0: sysctl@10001000 {
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compatible = "arm,sp810", "arm,primecell";
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reg = <0x10001000 0x1000>;
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clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
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clock-names = "refclk", "timclk", "apb_pclk";
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#clock-cells = <1>;
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clock-output-names = "timerclk0",
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"timerclk1",
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"timerclk2",
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"timerclk3";
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assigned-clocks = <&sp810_syscon0 0>,
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<&sp810_syscon0 1>,
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<&sp810_syscon0 2>,
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<&sp810_syscon0 3>;
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assigned-clock-parents = <&timclk>,
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<&timclk>,
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<&timclk>,
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<&timclk>;
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};
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i2c: i2c@10002000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "arm,versatile-i2c";
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reg = <0x10002000 0x1000>;
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rtc@68 {
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compatible = "dallas,ds1338";
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reg = <0x68>;
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};
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};
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serial0: serial@10009000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x10009000 0x1000>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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serial1: serial@1000a000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1000a000 0x1000>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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serial2: serial@1000b000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1000b000 0x1000>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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ssp: spi@1000d000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x1000d000 0x1000>;
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clocks = <&sspclk>, <&pclk>;
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clock-names = "SSPCLK", "apb_pclk";
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};
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wdog0: watchdog@1000f000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x1000f000 0x1000>;
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clocks = <&wdogclk>, <&pclk>;
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clock-names = "wdogclk", "apb_pclk";
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status = "disabled";
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};
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wdog1: watchdog@10010000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x10010000 0x1000>;
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clocks = <&wdogclk>, <&pclk>;
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clock-names = "wdogclk", "apb_pclk";
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status = "disabled";
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};
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timer01: timer@10011000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x10011000 0x1000>;
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clocks = <&sp810_syscon0 0>,
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<&sp810_syscon0 1>,
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<&pclk>;
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clock-names = "timerclk0",
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"timerclk1",
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"apb_pclk";
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};
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timer23: timer@10012000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x10012000 0x1000>;
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clocks = <&sp810_syscon0 2>,
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<&sp810_syscon0 3>,
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<&pclk>;
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clock-names = "timerclk2",
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"timerclk3",
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"apb_pclk";
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};
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gpio0: gpio@10013000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x10013000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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gpio1: gpio@10014000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x10014000 0x1000>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
clocks = <&pclk>;
|
||
|
|
clock-names = "apb_pclk";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpio2: gpio@10015000 {
|
||
|
|
compatible = "arm,pl061", "arm,primecell";
|
||
|
|
reg = <0x10015000 0x1000>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
clocks = <&pclk>;
|
||
|
|
clock-names = "apb_pclk";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* DVI serial bus control is at 10016000 */
|
||
|
|
|
||
|
|
rtc: rtc@10017000 {
|
||
|
|
compatible = "arm,pl031", "arm,primecell";
|
||
|
|
reg = <0x10017000 0x1000>;
|
||
|
|
clocks = <&pclk>;
|
||
|
|
clock-names = "apb_pclk";
|
||
|
|
};
|
||
|
|
|
||
|
|
timer45: timer@10018000 {
|
||
|
|
compatible = "arm,sp804", "arm,primecell";
|
||
|
|
reg = <0x10018000 0x1000>;
|
||
|
|
clocks = <&timclk>, <&timclk>, <&pclk>;
|
||
|
|
clock-names = "timerclk4", "timerclk5", "apb_pclk";
|
||
|
|
};
|
||
|
|
|
||
|
|
timer67: timer@10019000 {
|
||
|
|
compatible = "arm,sp804", "arm,primecell";
|
||
|
|
reg = <0x10019000 0x1000>;
|
||
|
|
clocks = <&timclk>, <&timclk>, <&pclk>;
|
||
|
|
clock-names = "timerclk6", "timerclk7", "apb_pclk";
|
||
|
|
};
|
||
|
|
|
||
|
|
sp810_syscon1: sysctl@1001a000 {
|
||
|
|
compatible = "arm,sp810", "arm,primecell";
|
||
|
|
reg = <0x1001a000 0x1000>;
|
||
|
|
clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
|
||
|
|
clock-names = "refclk", "timclk", "apb_pclk";
|
||
|
|
#clock-cells = <1>;
|
||
|
|
clock-output-names = "timerclk4",
|
||
|
|
"timerclk5",
|
||
|
|
"timerclk6",
|
||
|
|
"timerclk7";
|
||
|
|
assigned-clocks = <&sp810_syscon1 0>,
|
||
|
|
<&sp810_syscon1 1>,
|
||
|
|
<&sp810_syscon1 2>,
|
||
|
|
<&sp810_syscon1 3>;
|
||
|
|
assigned-clock-parents = <&timclk>,
|
||
|
|
<&timclk>,
|
||
|
|
<&timclk>,
|
||
|
|
<&timclk>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
/* These peripherals are inside the FPGA */
|
||
|
|
fpga {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
compatible = "simple-bus";
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
aaci: aaci@10004000 {
|
||
|
|
compatible = "arm,pl041", "arm,primecell";
|
||
|
|
reg = <0x10004000 0x1000>;
|
||
|
|
clocks = <&pclk>;
|
||
|
|
clock-names = "apb_pclk";
|
||
|
|
};
|
||
|
|
|
||
|
|
mmc: mmcsd@10005000 {
|
||
|
|
compatible = "arm,pl18x", "arm,primecell";
|
||
|
|
reg = <0x10005000 0x1000>;
|
||
|
|
|
||
|
|
/* Due to frequent FIFO overruns, use just 500 kHz */
|
||
|
|
max-frequency = <500000>;
|
||
|
|
bus-width = <4>;
|
||
|
|
cap-sd-highspeed;
|
||
|
|
cap-mmc-highspeed;
|
||
|
|
clocks = <&mclk>, <&pclk>;
|
||
|
|
clock-names = "mclk", "apb_pclk";
|
||
|
|
vmmc-supply = <&vmmc>;
|
||
|
|
cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
||
|
|
wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
kmi0: kmi@10006000 {
|
||
|
|
compatible = "arm,pl050", "arm,primecell";
|
||
|
|
reg = <0x10006000 0x1000>;
|
||
|
|
clocks = <&kmiclk>, <&pclk>;
|
||
|
|
clock-names = "KMIREFCLK", "apb_pclk";
|
||
|
|
};
|
||
|
|
|
||
|
|
kmi1: kmi@10007000 {
|
||
|
|
compatible = "arm,pl050", "arm,primecell";
|
||
|
|
reg = <0x10007000 0x1000>;
|
||
|
|
clocks = <&kmiclk>, <&pclk>;
|
||
|
|
clock-names = "KMIREFCLK", "apb_pclk";
|
||
|
|
};
|
||
|
|
|
||
|
|
serial3: serial@1000c000 {
|
||
|
|
compatible = "arm,pl011", "arm,primecell";
|
||
|
|
reg = <0x1000c000 0x1000>;
|
||
|
|
clocks = <&uartclk>, <&pclk>;
|
||
|
|
clock-names = "uartclk", "apb_pclk";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* These peripherals are inside the NEC ISSP */
|
||
|
|
issp {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
compatible = "simple-bus";
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
clcd: clcd@10020000 {
|
||
|
|
compatible = "arm,pl111", "arm,primecell";
|
||
|
|
reg = <0x10020000 0x1000>;
|
||
|
|
interrupt-names = "combined";
|
||
|
|
clocks = <&oscclk4>, <&pclk>;
|
||
|
|
clock-names = "clcdclk", "apb_pclk";
|
||
|
|
|
||
|
|
port {
|
||
|
|
clcd_pads: endpoint {
|
||
|
|
remote-endpoint = <&clcd_panel>;
|
||
|
|
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
panel {
|
||
|
|
compatible = "panel-dpi";
|
||
|
|
|
||
|
|
port {
|
||
|
|
clcd_panel: endpoint {
|
||
|
|
remote-endpoint = <&clcd_pads>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Standard 640x480 VGA timings */
|
||
|
|
panel-timing {
|
||
|
|
clock-frequency = <25175000>;
|
||
|
|
hactive = <640>;
|
||
|
|
hback-porch = <48>;
|
||
|
|
hfront-porch = <16>;
|
||
|
|
hsync-len = <96>;
|
||
|
|
vactive = <480>;
|
||
|
|
vback-porch = <33>;
|
||
|
|
vfront-porch = <10>;
|
||
|
|
vsync-len = <2>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|