130 lines
2.5 KiB
Plaintext
130 lines
2.5 KiB
Plaintext
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/*
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* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx1.dtsi"
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/ {
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model = "Armadeus APF9328";
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compatible = "armadeus,imx1-apf9328", "fsl,imx1";
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chosen {
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stdout-path = &uart1;
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};
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memory {
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reg = <0x08000000 0x00800000>;
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};
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};
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&i2c {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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uart-has-rtscts;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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uart-has-rtscts;
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status = "okay";
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};
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&weim {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_weim>;
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status = "okay";
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nor: nor@0,0 {
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compatible = "cfi-flash";
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reg = <0 0x00000000 0x02000000>;
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bank-width = <2>;
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fsl,weim-cs-timing = <0x00330e04 0x00000d01>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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eth: eth@4,c00000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eth>;
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compatible = "davicom,dm9000";
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reg = <
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4 0x00c00000 0x2
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4 0x00c00002 0x2
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>;
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interrupt-parent = <&gpio2>;
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interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
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fsl,weim-cs-timing = <0x0000c700 0x19190d01>;
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};
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};
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&iomuxc {
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imx1-apf9328 {
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pinctrl_eth: ethgrp {
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fsl,pins = <
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MX1_PAD_SIM_SVEN__GPIO2_14 0x0
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>;
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};
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pinctrl_i2c: i2cgrp {
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fsl,pins = <
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MX1_PAD_I2C_SCL__I2C_SCL 0x0
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MX1_PAD_I2C_SDA__I2C_SDA 0x0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX1_PAD_UART1_TXD__UART1_TXD 0x0
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MX1_PAD_UART1_RXD__UART1_RXD 0x0
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MX1_PAD_UART1_CTS__UART1_CTS 0x0
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MX1_PAD_UART1_RTS__UART1_RTS 0x0
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX1_PAD_UART2_TXD__UART2_TXD 0x0
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MX1_PAD_UART2_RXD__UART2_RXD 0x0
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MX1_PAD_UART2_CTS__UART2_CTS 0x0
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MX1_PAD_UART2_RTS__UART2_RTS 0x0
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>;
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};
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pinctrl_weim: weimgrp {
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fsl,pins = <
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MX1_PAD_A0__A0 0x0
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MX1_PAD_A16__A16 0x0
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MX1_PAD_A17__A17 0x0
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MX1_PAD_A18__A18 0x0
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MX1_PAD_A19__A19 0x0
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MX1_PAD_A20__A20 0x0
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MX1_PAD_A21__A21 0x0
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MX1_PAD_A22__A22 0x0
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MX1_PAD_A23__A23 0x0
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MX1_PAD_A24__A24 0x0
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MX1_PAD_BCLK__BCLK 0x0
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MX1_PAD_CS4__CS4 0x0
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MX1_PAD_DTACK__DTACK 0x0
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MX1_PAD_ECB__ECB 0x0
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MX1_PAD_LBA__LBA 0x0
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>;
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};
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};
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};
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