813 lines
20 KiB
Plaintext
813 lines
20 KiB
Plaintext
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "skeleton.dtsi"
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#include "imx53-pinfunc.h"
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#include <dt-bindings/clock/imx5-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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aliases {
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ethernet0 = &fec;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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gpio6 = &gpio7;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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mmc0 = &esdhc1;
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mmc1 = &esdhc2;
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mmc2 = &esdhc3;
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mmc3 = &esdhc4;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &cspi;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0x0>;
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clocks = <&clks IMX5_CLK_ARM>;
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clock-latency = <61036>;
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voltage-tolerance = <5>;
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operating-points = <
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/* kHz */
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166666 850000
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400000 900000
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800000 1050000
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1000000 1200000
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1200000 1300000
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>;
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};
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};
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display-subsystem {
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compatible = "fsl,imx-display-subsystem";
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ports = <&ipu_di0>, <&ipu_di1>;
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};
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tzic: tz-interrupt-controller@0fffc000 {
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compatible = "fsl,imx53-tzic", "fsl,tzic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x0fffc000 0x4000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ckil {
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compatible = "fsl,imx-ckil", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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ckih1 {
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compatible = "fsl,imx-ckih1", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <22579200>;
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};
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ckih2 {
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compatible = "fsl,imx-ckih2", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&tzic>;
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ranges;
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sata: sata@10000000 {
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compatible = "fsl,imx53-ahci";
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reg = <0x10000000 0x1000>;
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interrupts = <28>;
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clocks = <&clks IMX5_CLK_SATA_GATE>,
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<&clks IMX5_CLK_SATA_REF>,
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<&clks IMX5_CLK_AHB>;
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clock-names = "sata", "sata_ref", "ahb";
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status = "disabled";
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};
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ipu: ipu@18000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-ipu";
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reg = <0x18000000 0x08000000>;
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interrupts = <11 10>;
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clocks = <&clks IMX5_CLK_IPU_GATE>,
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<&clks IMX5_CLK_IPU_DI0_GATE>,
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<&clks IMX5_CLK_IPU_DI1_GATE>;
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clock-names = "bus", "di0", "di1";
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resets = <&src 2>;
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ipu_csi0: port@0 {
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reg = <0>;
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};
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ipu_csi1: port@1 {
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reg = <1>;
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};
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ipu_di0: port@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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ipu_di0_disp0: endpoint@0 {
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reg = <0>;
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};
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ipu_di0_lvds0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&lvds0_in>;
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};
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};
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ipu_di1: port@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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ipu_di1_disp1: endpoint@0 {
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reg = <0>;
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};
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ipu_di1_lvds1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&lvds1_in>;
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};
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ipu_di1_tve: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&tve_in>;
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};
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};
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};
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aips@50000000 { /* AIPS1 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x10000000>;
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ranges;
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spba@50000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x40000>;
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ranges;
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esdhc1: esdhc@50004000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50004000 0x4000>;
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interrupts = <1>;
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clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC1_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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esdhc2: esdhc@50008000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50008000 0x4000>;
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interrupts = <2>;
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clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC2_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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uart3: serial@5000c000 {
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compatible = "fsl,imx53-uart", "fsl,imx21-uart";
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reg = <0x5000c000 0x4000>;
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interrupts = <33>;
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clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
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<&clks IMX5_CLK_UART3_PER_GATE>;
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clock-names = "ipg", "per";
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dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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ecspi1: ecspi@50010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
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reg = <0x50010000 0x4000>;
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interrupts = <36>;
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clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
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<&clks IMX5_CLK_ECSPI1_PER_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ssi2: ssi@50014000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx53-ssi",
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"fsl,imx51-ssi",
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"fsl,imx21-ssi";
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reg = <0x50014000 0x4000>;
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interrupts = <30>;
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clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
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<&clks IMX5_CLK_SSI2_ROOT_GATE>;
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clock-names = "ipg", "baud";
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dmas = <&sdma 24 1 0>,
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<&sdma 25 1 0>;
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dma-names = "rx", "tx";
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fsl,fifo-depth = <15>;
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status = "disabled";
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};
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esdhc3: esdhc@50020000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50020000 0x4000>;
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interrupts = <3>;
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clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC3_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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esdhc4: esdhc@50024000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50024000 0x4000>;
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interrupts = <4>;
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clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC4_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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};
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aipstz1: bridge@53f00000 {
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compatible = "fsl,imx53-aipstz";
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reg = <0x53f00000 0x60>;
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};
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usbphy0: usbphy@0 {
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compatible = "usb-nop-xceiv";
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clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
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clock-names = "main_clk";
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status = "okay";
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};
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usbphy1: usbphy@1 {
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compatible = "usb-nop-xceiv";
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clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
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clock-names = "main_clk";
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status = "okay";
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};
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usbotg: usb@53f80000 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80000 0x0200>;
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interrupts = <18>;
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clocks = <&clks IMX5_CLK_USBOH3_GATE>;
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fsl,usbmisc = <&usbmisc 0>;
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fsl,usbphy = <&usbphy0>;
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status = "disabled";
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};
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usbh1: usb@53f80200 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80200 0x0200>;
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interrupts = <14>;
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clocks = <&clks IMX5_CLK_USBOH3_GATE>;
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fsl,usbmisc = <&usbmisc 1>;
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fsl,usbphy = <&usbphy1>;
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dr_mode = "host";
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status = "disabled";
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};
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usbh2: usb@53f80400 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80400 0x0200>;
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interrupts = <16>;
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clocks = <&clks IMX5_CLK_USBOH3_GATE>;
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fsl,usbmisc = <&usbmisc 2>;
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dr_mode = "host";
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status = "disabled";
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};
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usbh3: usb@53f80600 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80600 0x0200>;
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interrupts = <17>;
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clocks = <&clks IMX5_CLK_USBOH3_GATE>;
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fsl,usbmisc = <&usbmisc 3>;
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dr_mode = "host";
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status = "disabled";
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};
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usbmisc: usbmisc@53f80800 {
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#index-cells = <1>;
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compatible = "fsl,imx53-usbmisc";
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reg = <0x53f80800 0x200>;
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clocks = <&clks IMX5_CLK_USBOH3_GATE>;
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};
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gpio1: gpio@53f84000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f84000 0x4000>;
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interrupts = <50 51>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@53f88000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f88000 0x4000>;
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interrupts = <52 53>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpio3: gpio@53f8c000 {
|
||
|
|
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||
|
|
reg = <0x53f8c000 0x4000>;
|
||
|
|
interrupts = <54 55>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpio4: gpio@53f90000 {
|
||
|
|
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||
|
|
reg = <0x53f90000 0x4000>;
|
||
|
|
interrupts = <56 57>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
kpp: kpp@53f94000 {
|
||
|
|
compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
|
||
|
|
reg = <0x53f94000 0x4000>;
|
||
|
|
interrupts = <60>;
|
||
|
|
clocks = <&clks IMX5_CLK_DUMMY>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
wdog1: wdog@53f98000 {
|
||
|
|
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||
|
|
reg = <0x53f98000 0x4000>;
|
||
|
|
interrupts = <58>;
|
||
|
|
clocks = <&clks IMX5_CLK_DUMMY>;
|
||
|
|
};
|
||
|
|
|
||
|
|
wdog2: wdog@53f9c000 {
|
||
|
|
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||
|
|
reg = <0x53f9c000 0x4000>;
|
||
|
|
interrupts = <59>;
|
||
|
|
clocks = <&clks IMX5_CLK_DUMMY>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpt: timer@53fa0000 {
|
||
|
|
compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
|
||
|
|
reg = <0x53fa0000 0x4000>;
|
||
|
|
interrupts = <39>;
|
||
|
|
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_GPT_HF_GATE>;
|
||
|
|
clock-names = "ipg", "per";
|
||
|
|
};
|
||
|
|
|
||
|
|
iomuxc: iomuxc@53fa8000 {
|
||
|
|
compatible = "fsl,imx53-iomuxc";
|
||
|
|
reg = <0x53fa8000 0x4000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpr: iomuxc-gpr@53fa8000 {
|
||
|
|
compatible = "fsl,imx53-iomuxc-gpr", "syscon";
|
||
|
|
reg = <0x53fa8000 0xc>;
|
||
|
|
};
|
||
|
|
|
||
|
|
ldb: ldb@53fa8008 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "fsl,imx53-ldb";
|
||
|
|
reg = <0x53fa8008 0x4>;
|
||
|
|
gpr = <&gpr>;
|
||
|
|
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
|
||
|
|
<&clks IMX5_CLK_LDB_DI1_SEL>,
|
||
|
|
<&clks IMX5_CLK_IPU_DI0_SEL>,
|
||
|
|
<&clks IMX5_CLK_IPU_DI1_SEL>,
|
||
|
|
<&clks IMX5_CLK_LDB_DI0_GATE>,
|
||
|
|
<&clks IMX5_CLK_LDB_DI1_GATE>;
|
||
|
|
clock-names = "di0_pll", "di1_pll",
|
||
|
|
"di0_sel", "di1_sel",
|
||
|
|
"di0", "di1";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
lvds-channel@0 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
port@0 {
|
||
|
|
reg = <0>;
|
||
|
|
|
||
|
|
lvds0_in: endpoint {
|
||
|
|
remote-endpoint = <&ipu_di0_lvds0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
lvds-channel@1 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <1>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
port@1 {
|
||
|
|
reg = <1>;
|
||
|
|
|
||
|
|
lvds1_in: endpoint {
|
||
|
|
remote-endpoint = <&ipu_di1_lvds1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pwm1: pwm@53fb4000 {
|
||
|
|
#pwm-cells = <2>;
|
||
|
|
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||
|
|
reg = <0x53fb4000 0x4000>;
|
||
|
|
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_PWM1_HF_GATE>;
|
||
|
|
clock-names = "ipg", "per";
|
||
|
|
interrupts = <61>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pwm2: pwm@53fb8000 {
|
||
|
|
#pwm-cells = <2>;
|
||
|
|
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||
|
|
reg = <0x53fb8000 0x4000>;
|
||
|
|
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_PWM2_HF_GATE>;
|
||
|
|
clock-names = "ipg", "per";
|
||
|
|
interrupts = <94>;
|
||
|
|
};
|
||
|
|
|
||
|
|
uart1: serial@53fbc000 {
|
||
|
|
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||
|
|
reg = <0x53fbc000 0x4000>;
|
||
|
|
interrupts = <31>;
|
||
|
|
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_UART1_PER_GATE>;
|
||
|
|
clock-names = "ipg", "per";
|
||
|
|
dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart2: serial@53fc0000 {
|
||
|
|
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||
|
|
reg = <0x53fc0000 0x4000>;
|
||
|
|
interrupts = <32>;
|
||
|
|
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_UART2_PER_GATE>;
|
||
|
|
clock-names = "ipg", "per";
|
||
|
|
dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
can1: can@53fc8000 {
|
||
|
|
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||
|
|
reg = <0x53fc8000 0x4000>;
|
||
|
|
interrupts = <82>;
|
||
|
|
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_CAN1_SERIAL_GATE>;
|
||
|
|
clock-names = "ipg", "per";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
can2: can@53fcc000 {
|
||
|
|
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||
|
|
reg = <0x53fcc000 0x4000>;
|
||
|
|
interrupts = <83>;
|
||
|
|
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_CAN2_SERIAL_GATE>;
|
||
|
|
clock-names = "ipg", "per";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
src: src@53fd0000 {
|
||
|
|
compatible = "fsl,imx53-src", "fsl,imx51-src";
|
||
|
|
reg = <0x53fd0000 0x4000>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
clks: ccm@53fd4000{
|
||
|
|
compatible = "fsl,imx53-ccm";
|
||
|
|
reg = <0x53fd4000 0x4000>;
|
||
|
|
interrupts = <0 71 0x04 0 72 0x04>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpio5: gpio@53fdc000 {
|
||
|
|
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||
|
|
reg = <0x53fdc000 0x4000>;
|
||
|
|
interrupts = <103 104>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpio6: gpio@53fe0000 {
|
||
|
|
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||
|
|
reg = <0x53fe0000 0x4000>;
|
||
|
|
interrupts = <105 106>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpio7: gpio@53fe4000 {
|
||
|
|
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||
|
|
reg = <0x53fe4000 0x4000>;
|
||
|
|
interrupts = <107 108>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c3: i2c@53fec000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||
|
|
reg = <0x53fec000 0x4000>;
|
||
|
|
interrupts = <64>;
|
||
|
|
clocks = <&clks IMX5_CLK_I2C3_GATE>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart4: serial@53ff0000 {
|
||
|
|
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||
|
|
reg = <0x53ff0000 0x4000>;
|
||
|
|
interrupts = <13>;
|
||
|
|
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_UART4_PER_GATE>;
|
||
|
|
clock-names = "ipg", "per";
|
||
|
|
dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
aips@60000000 { /* AIPS2 */
|
||
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
reg = <0x60000000 0x10000000>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
aipstz2: bridge@63f00000 {
|
||
|
|
compatible = "fsl,imx53-aipstz";
|
||
|
|
reg = <0x63f00000 0x60>;
|
||
|
|
};
|
||
|
|
|
||
|
|
iim: iim@63f98000 {
|
||
|
|
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
|
||
|
|
reg = <0x63f98000 0x4000>;
|
||
|
|
interrupts = <69>;
|
||
|
|
clocks = <&clks IMX5_CLK_IIM_GATE>;
|
||
|
|
};
|
||
|
|
|
||
|
|
uart5: serial@63f90000 {
|
||
|
|
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||
|
|
reg = <0x63f90000 0x4000>;
|
||
|
|
interrupts = <86>;
|
||
|
|
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_UART5_PER_GATE>;
|
||
|
|
clock-names = "ipg", "per";
|
||
|
|
dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
owire: owire@63fa4000 {
|
||
|
|
compatible = "fsl,imx53-owire", "fsl,imx21-owire";
|
||
|
|
reg = <0x63fa4000 0x4000>;
|
||
|
|
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
ecspi2: ecspi@63fac000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
||
|
|
reg = <0x63fac000 0x4000>;
|
||
|
|
interrupts = <37>;
|
||
|
|
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
|
||
|
|
clock-names = "ipg", "per";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sdma: sdma@63fb0000 {
|
||
|
|
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
|
||
|
|
reg = <0x63fb0000 0x4000>;
|
||
|
|
interrupts = <6>;
|
||
|
|
clocks = <&clks IMX5_CLK_SDMA_GATE>,
|
||
|
|
<&clks IMX5_CLK_SDMA_GATE>;
|
||
|
|
clock-names = "ipg", "ahb";
|
||
|
|
#dma-cells = <3>;
|
||
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||
|
|
};
|
||
|
|
|
||
|
|
cspi: cspi@63fc0000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
|
||
|
|
reg = <0x63fc0000 0x4000>;
|
||
|
|
interrupts = <38>;
|
||
|
|
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_CSPI_IPG_GATE>;
|
||
|
|
clock-names = "ipg", "per";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c2: i2c@63fc4000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||
|
|
reg = <0x63fc4000 0x4000>;
|
||
|
|
interrupts = <63>;
|
||
|
|
clocks = <&clks IMX5_CLK_I2C2_GATE>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c1: i2c@63fc8000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||
|
|
reg = <0x63fc8000 0x4000>;
|
||
|
|
interrupts = <62>;
|
||
|
|
clocks = <&clks IMX5_CLK_I2C1_GATE>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
ssi1: ssi@63fcc000 {
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
|
||
|
|
"fsl,imx21-ssi";
|
||
|
|
reg = <0x63fcc000 0x4000>;
|
||
|
|
interrupts = <29>;
|
||
|
|
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_SSI1_ROOT_GATE>;
|
||
|
|
clock-names = "ipg", "baud";
|
||
|
|
dmas = <&sdma 28 0 0>,
|
||
|
|
<&sdma 29 0 0>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
fsl,fifo-depth = <15>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
audmux: audmux@63fd0000 {
|
||
|
|
compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
|
||
|
|
reg = <0x63fd0000 0x4000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
nfc: nand@63fdb000 {
|
||
|
|
compatible = "fsl,imx53-nand";
|
||
|
|
reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
|
||
|
|
interrupts = <8>;
|
||
|
|
clocks = <&clks IMX5_CLK_NFC_GATE>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
ssi3: ssi@63fe8000 {
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
|
||
|
|
"fsl,imx21-ssi";
|
||
|
|
reg = <0x63fe8000 0x4000>;
|
||
|
|
interrupts = <96>;
|
||
|
|
clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_SSI3_ROOT_GATE>;
|
||
|
|
clock-names = "ipg", "baud";
|
||
|
|
dmas = <&sdma 46 0 0>,
|
||
|
|
<&sdma 47 0 0>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
fsl,fifo-depth = <15>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
fec: ethernet@63fec000 {
|
||
|
|
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
|
||
|
|
reg = <0x63fec000 0x4000>;
|
||
|
|
interrupts = <87>;
|
||
|
|
clocks = <&clks IMX5_CLK_FEC_GATE>,
|
||
|
|
<&clks IMX5_CLK_FEC_GATE>,
|
||
|
|
<&clks IMX5_CLK_FEC_GATE>;
|
||
|
|
clock-names = "ipg", "ahb", "ptp";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
tve: tve@63ff0000 {
|
||
|
|
compatible = "fsl,imx53-tve";
|
||
|
|
reg = <0x63ff0000 0x1000>;
|
||
|
|
interrupts = <92>;
|
||
|
|
clocks = <&clks IMX5_CLK_TVE_GATE>,
|
||
|
|
<&clks IMX5_CLK_IPU_DI1_SEL>;
|
||
|
|
clock-names = "tve", "di_sel";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
port {
|
||
|
|
tve_in: endpoint {
|
||
|
|
remote-endpoint = <&ipu_di1_tve>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
vpu: vpu@63ff4000 {
|
||
|
|
compatible = "fsl,imx53-vpu", "cnm,coda7541";
|
||
|
|
reg = <0x63ff4000 0x1000>;
|
||
|
|
interrupts = <9>;
|
||
|
|
clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
|
||
|
|
<&clks IMX5_CLK_VPU_GATE>;
|
||
|
|
clock-names = "per", "ahb";
|
||
|
|
resets = <&src 1>;
|
||
|
|
iram = <&ocram>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sahara: crypto@63ff8000 {
|
||
|
|
compatible = "fsl,imx53-sahara";
|
||
|
|
reg = <0x63ff8000 0x4000>;
|
||
|
|
interrupts = <19 20>;
|
||
|
|
clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_SAHARA_IPG_GATE>;
|
||
|
|
clock-names = "ipg", "ahb";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
ocram: sram@f8000000 {
|
||
|
|
compatible = "mmio-sram";
|
||
|
|
reg = <0xf8000000 0x20000>;
|
||
|
|
clocks = <&clks IMX5_CLK_OCRAM>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pmu {
|
||
|
|
compatible = "arm,cortex-a8-pmu";
|
||
|
|
interrupts = <77>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|