tegrakernel/kernel/kernel-4.9/arch/arm/boot/dts/imx6qdl-apf6.dtsi

/*
 * Copyright 2015 Armadeus Systems
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of
 *     the License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
 *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii";
	phy-reset-duration = <10>;
	phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
	status = "okay";
};

/* Bluetooth */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

/* Wi-Fi */
&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	non-removable;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@2 {
		compatible = "ti,wl1271";
		reg = <2>;
		interrupt-parent = <&gpio2>;
		interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
		ref-clock-frequency = <38400000>;
		tcxo-clock-frequency = <38400000>;
	};
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	status = "okay";
};

&iomuxc {
	apf6 {
		pinctrl_enet: enetgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b8b0
				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
				MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24	0x130b0
				MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x130b0
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x13030
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1f030
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1f030
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x13030
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b0
				MX6QDL_PAD_SD4_DAT5__UART2_RTS_B	0x1b0b0
				MX6QDL_PAD_SD4_DAT6__UART2_CTS_B	0x1b0b0
				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b0
				MX6QDL_PAD_SD4_DAT3__GPIO2_IO11		0x130b0 /* BT_EN */
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX6QDL_PAD_SD1_CMD__SD1_CMD	0x17059
				MX6QDL_PAD_SD1_CLK__SD1_CLK	0x10059
				MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x17059
				MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x17059
				MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x17059
				MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x17059
				MX6QDL_PAD_SD4_DAT0__GPIO2_IO08	0x1b0b0 /* WL_EN */
				MX6QDL_PAD_SD4_DAT2__GPIO2_IO10	0x1b0b0 /* WL_IRQ */
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
				MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
				MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
				MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
				MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
				MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
			>;
		};
	};
};