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tegrakernel/kernel/kernel-4.9/arch/arm/boot/dts/imx6qdl-udoo.dtsi

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initial commit tegra kernel 32.6.1
2022-02-16 09:13:02 -06:00
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/ {
aliases {
backlight = &backlight;
panelchan = &panelchan;
panel7 = &panel7;
touchscreenp7 = &touchscreenp7;
};
chosen {
stdout-path = &uart2;
};
backlight: backlight {
compatible = "gpio-backlight";
gpios = <&gpio1 4 0>;
default-on;
status = "disabled";
};
memory {
reg = <0x10000000 0x40000000>;
};
panel7: panel7 {
/*
* in reality it is a -20t (parallel) model,
* but with LVDS bridge chip attached,
* so it is equivalent to -19t model in drive
* characteristics
*/
compatible = "urt,umsh-8596md-19t";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel>;
power-supply = <&reg_panel>;
backlight = <&backlight>;
status = "disabled";
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_h1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
gpio = <&gpio7 12 0>;
};
reg_panel: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "lcd_panel";
enable-active-high;
gpio = <&gpio1 2 0>;
};
};
sound {
compatible = "fsl,imx6q-udoo-ac97",
"fsl,imx-audio-ac97";
model = "fsl,imx6q-udoo-ac97";
audio-cpu = <&ssi1>;
audio-routing =
"RX", "Mic Jack",
"Headphone Jack", "TX";
mux-int-port = <1>;
mux-ext-port = <6>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
touchscreenp7: touchscreenp7@55 {
compatible = "sitronix,st1232";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touchscreenp7>;
reg = <0x55>;
interrupt-parent = <&gpio1>;
interrupts = <13 8>;
gpios = <&gpio1 15 0>;
status = "disabled";
};
};
&iomuxc {
imx6q-udoo {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1
>;
};
pinctrl_panel: panelgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70
>;
};
pinctrl_touchscreenp7: touchscreenp7grp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_usbh: usbhgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
pinctrl_ac97_running: ac97running {
fsl,pins = <
MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0
MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0
MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b0b0
MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b0b0
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
>;
};
pinctrl_ac97_warm_reset: ac97warmreset {
fsl,pins = <
MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0
MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0
MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b0b0
MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b0b0
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
>;
};
pinctrl_ac97_reset: ac97reset {
fsl,pins = <
MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0
MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b0b0
MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b0b0
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
>;
};
};
};
&ldb {
status = "okay";
panelchan: lvds-channel@0 {
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh>;
vbus-supply = <&reg_usb_h1_vbus>;
clocks = <&clks IMX6QDL_CLK_CKO>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
non-removable;
status = "okay";
};
&audmux {
status = "okay";
};
&ssi1 {
cell-index = <0>;
fsl,mode = "ac97-slave";
pinctrl-names = "ac97-running", "ac97-reset", "ac97-warm-reset";
pinctrl-0 = <&pinctrl_ac97_running>;
pinctrl-1 = <&pinctrl_ac97_reset>;
pinctrl-2 = <&pinctrl_ac97_warm_reset>;
ac97-gpios = <&gpio4 19 0 &gpio4 18 0 &gpio2 30 0>;
status = "okay";
};