316 lines
8.9 KiB
C
316 lines
8.9 KiB
C
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/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/mm.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/opcodes.h>
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#include <trace/events/kvm.h>
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#include "trace.h"
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#define VCPU_NR_MODES 6
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#define VCPU_REG_OFFSET_USR 0
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#define VCPU_REG_OFFSET_FIQ 1
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#define VCPU_REG_OFFSET_IRQ 2
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#define VCPU_REG_OFFSET_SVC 3
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#define VCPU_REG_OFFSET_ABT 4
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#define VCPU_REG_OFFSET_UND 5
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#define REG_OFFSET(_reg) \
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(offsetof(struct kvm_regs, _reg) / sizeof(u32))
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#define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
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static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = {
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/* USR/SYS Registers */
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[VCPU_REG_OFFSET_USR] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14),
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},
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/* FIQ Registers */
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[VCPU_REG_OFFSET_FIQ] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7),
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REG_OFFSET(fiq_regs[0]), /* r8 */
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REG_OFFSET(fiq_regs[1]), /* r9 */
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REG_OFFSET(fiq_regs[2]), /* r10 */
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REG_OFFSET(fiq_regs[3]), /* r11 */
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REG_OFFSET(fiq_regs[4]), /* r12 */
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REG_OFFSET(fiq_regs[5]), /* r13 */
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REG_OFFSET(fiq_regs[6]), /* r14 */
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},
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/* IRQ Registers */
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[VCPU_REG_OFFSET_IRQ] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(irq_regs[0]), /* r13 */
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REG_OFFSET(irq_regs[1]), /* r14 */
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},
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/* SVC Registers */
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[VCPU_REG_OFFSET_SVC] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(svc_regs[0]), /* r13 */
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REG_OFFSET(svc_regs[1]), /* r14 */
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},
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/* ABT Registers */
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[VCPU_REG_OFFSET_ABT] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(abt_regs[0]), /* r13 */
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REG_OFFSET(abt_regs[1]), /* r14 */
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},
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/* UND Registers */
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[VCPU_REG_OFFSET_UND] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(und_regs[0]), /* r13 */
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REG_OFFSET(und_regs[1]), /* r14 */
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},
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};
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/*
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* Return a pointer to the register number valid in the current mode of
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* the virtual CPU.
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*/
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unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
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{
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unsigned long *reg_array = (unsigned long *)&vcpu->arch.ctxt.gp_regs;
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unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
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switch (mode) {
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case USR_MODE...SVC_MODE:
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mode &= ~MODE32_BIT; /* 0 ... 3 */
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break;
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case ABT_MODE:
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mode = VCPU_REG_OFFSET_ABT;
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break;
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case UND_MODE:
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mode = VCPU_REG_OFFSET_UND;
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break;
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case SYSTEM_MODE:
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mode = VCPU_REG_OFFSET_USR;
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break;
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default:
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BUG();
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}
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return reg_array + vcpu_reg_offsets[mode][reg_num];
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}
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/*
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* Return the SPSR for the current mode of the virtual CPU.
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*/
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unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu)
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{
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unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
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switch (mode) {
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case SVC_MODE:
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return &vcpu->arch.ctxt.gp_regs.KVM_ARM_SVC_spsr;
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case ABT_MODE:
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return &vcpu->arch.ctxt.gp_regs.KVM_ARM_ABT_spsr;
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case UND_MODE:
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return &vcpu->arch.ctxt.gp_regs.KVM_ARM_UND_spsr;
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case IRQ_MODE:
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return &vcpu->arch.ctxt.gp_regs.KVM_ARM_IRQ_spsr;
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case FIQ_MODE:
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return &vcpu->arch.ctxt.gp_regs.KVM_ARM_FIQ_spsr;
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default:
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BUG();
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}
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}
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/******************************************************************************
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* Inject exceptions into the guest
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*/
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static u32 exc_vector_base(struct kvm_vcpu *vcpu)
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{
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u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
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u32 vbar = vcpu_cp15(vcpu, c12_VBAR);
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if (sctlr & SCTLR_V)
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return 0xffff0000;
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else /* always have security exceptions */
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return vbar;
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}
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/*
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* Switch to an exception mode, updating both CPSR and SPSR. Follow
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* the logic described in AArch32.EnterMode() from the ARMv8 ARM.
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*/
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static void kvm_update_psr(struct kvm_vcpu *vcpu, unsigned long mode)
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{
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unsigned long cpsr = *vcpu_cpsr(vcpu);
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u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
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*vcpu_cpsr(vcpu) = (cpsr & ~MODE_MASK) | mode;
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switch (mode) {
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case FIQ_MODE:
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*vcpu_cpsr(vcpu) |= PSR_F_BIT;
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/* Fall through */
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case ABT_MODE:
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case IRQ_MODE:
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*vcpu_cpsr(vcpu) |= PSR_A_BIT;
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/* Fall through */
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default:
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*vcpu_cpsr(vcpu) |= PSR_I_BIT;
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}
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*vcpu_cpsr(vcpu) &= ~(PSR_IT_MASK | PSR_J_BIT | PSR_E_BIT | PSR_T_BIT);
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if (sctlr & SCTLR_TE)
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*vcpu_cpsr(vcpu) |= PSR_T_BIT;
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if (sctlr & SCTLR_EE)
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*vcpu_cpsr(vcpu) |= PSR_E_BIT;
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/* Note: These now point to the mode banked copies */
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*vcpu_spsr(vcpu) = cpsr;
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}
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/**
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* kvm_inject_undefined - inject an undefined exception into the guest
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* @vcpu: The VCPU to receive the undefined exception
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*
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* Modelled after TakeUndefInstrException() pseudocode.
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*/
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void kvm_inject_undefined(struct kvm_vcpu *vcpu)
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{
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unsigned long cpsr = *vcpu_cpsr(vcpu);
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bool is_thumb = (cpsr & PSR_T_BIT);
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u32 vect_offset = 4;
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u32 return_offset = (is_thumb) ? 2 : 4;
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kvm_update_psr(vcpu, UND_MODE);
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*vcpu_reg(vcpu, 14) = *vcpu_pc(vcpu) + return_offset;
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/* Branch to exception vector */
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*vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset;
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}
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/*
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* Modelled after TakeDataAbortException() and TakePrefetchAbortException
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* pseudocode.
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*/
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static void inject_abt(struct kvm_vcpu *vcpu, bool is_pabt, unsigned long addr)
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{
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u32 vect_offset;
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u32 return_offset = (is_pabt) ? 4 : 8;
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bool is_lpae;
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kvm_update_psr(vcpu, ABT_MODE);
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*vcpu_reg(vcpu, 14) = *vcpu_pc(vcpu) + return_offset;
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if (is_pabt)
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vect_offset = 12;
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else
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vect_offset = 16;
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/* Branch to exception vector */
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*vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset;
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if (is_pabt) {
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/* Set IFAR and IFSR */
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vcpu_cp15(vcpu, c6_IFAR) = addr;
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is_lpae = (vcpu_cp15(vcpu, c2_TTBCR) >> 31);
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/* Always give debug fault for now - should give guest a clue */
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if (is_lpae)
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vcpu_cp15(vcpu, c5_IFSR) = 1 << 9 | 0x22;
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else
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vcpu_cp15(vcpu, c5_IFSR) = 2;
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} else { /* !iabt */
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/* Set DFAR and DFSR */
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vcpu_cp15(vcpu, c6_DFAR) = addr;
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is_lpae = (vcpu_cp15(vcpu, c2_TTBCR) >> 31);
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/* Always give debug fault for now - should give guest a clue */
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if (is_lpae)
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vcpu_cp15(vcpu, c5_DFSR) = 1 << 9 | 0x22;
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else
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vcpu_cp15(vcpu, c5_DFSR) = 2;
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}
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}
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/**
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* kvm_inject_dabt - inject a data abort into the guest
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* @vcpu: The VCPU to receive the undefined exception
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* @addr: The address to report in the DFAR
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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inject_abt(vcpu, false, addr);
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}
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/**
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* kvm_inject_pabt - inject a prefetch abort into the guest
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* @vcpu: The VCPU to receive the undefined exception
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* @addr: The address to report in the DFAR
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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inject_abt(vcpu, true, addr);
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}
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/**
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* kvm_inject_vabt - inject an async abort / SError into the guest
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* @vcpu: The VCPU to receive the exception
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_vabt(struct kvm_vcpu *vcpu)
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{
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vcpu_set_hcr(vcpu, vcpu_get_hcr(vcpu) | HCR_VA);
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}
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