323 lines
19 KiB
C
323 lines
19 KiB
C
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/*
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* DRA7xx CM1 instance offset macros
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
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*
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* Generated by code originally written by:
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* Paul Walmsley (paul@pwsan.com)
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* Rajendra Nayak (rnayak@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
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#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
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/* CM1 base address */
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#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
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#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \
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OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
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/* CM_CORE_AON instances */
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#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
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#define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
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#define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
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#define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
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#define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
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#define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
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#define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
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#define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
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#define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
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#define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700
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#define DRA7XX_CM_CORE_AON_RTC_INST 0x0740
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#define DRA7XX_CM_CORE_AON_VPE_INST 0x0760
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#define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00
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#define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00
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/* CM_CORE_AON clockdomain register offsets (from instance start) */
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#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
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#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000
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#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 0x0000
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#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 0x0040
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#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000
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#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000
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#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000
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#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000
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#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000
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#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000
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#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000
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/* CM_CORE_AON */
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/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
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#define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000
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#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
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#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
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#define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec
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#define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0
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#define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4
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#define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8
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#define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc
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/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
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#define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000
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#define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000)
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#define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008
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#define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008)
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#define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010
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#define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
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#define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020)
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#define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
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#define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024)
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#define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
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#define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028)
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#define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
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#define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c)
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#define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
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#define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030)
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#define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
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#define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034)
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#define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
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#define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038)
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#define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
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#define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c)
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#define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
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#define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040)
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#define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
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#define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044)
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#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
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#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
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#define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
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#define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050)
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#define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
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#define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054)
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#define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
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#define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058)
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#define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
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#define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c)
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#define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
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#define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060)
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#define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
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#define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064)
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#define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
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#define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068)
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#define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
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#define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c)
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#define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
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#define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070)
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#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
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#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
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#define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
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#define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c)
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#define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
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#define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
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#define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
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#define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
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#define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
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#define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
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#define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
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#define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
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#define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0
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#define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0)
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#define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4
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#define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4)
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#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
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#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
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#define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
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#define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
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#define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
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#define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
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#define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
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#define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
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#define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
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#define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
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#define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
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#define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
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#define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
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#define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
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#define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
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#define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
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#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
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#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
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#define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110
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#define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110)
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#define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114
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#define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114)
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#define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118
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#define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118)
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#define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c
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#define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c)
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#define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120
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#define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120)
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#define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124
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#define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124)
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#define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128
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#define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128)
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#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c
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#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130
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#define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134
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#define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134)
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#define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138
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#define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138)
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#define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c
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#define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c)
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#define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140
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#define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140)
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#define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144
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#define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144)
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#define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148
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#define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148)
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#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c
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#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150
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#define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154
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#define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154)
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#define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
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#define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
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#define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
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#define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180
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#define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184
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#define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184)
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#define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188
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#define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188)
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#define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c
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#define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c)
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#define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190
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#define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190)
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#define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194
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#define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194)
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#define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198
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#define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198)
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#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c
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#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0
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#define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4
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#define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4)
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#define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8
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#define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8)
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#define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac
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#define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac)
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#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0
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#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0)
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#define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4
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#define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4)
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#define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8
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#define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8)
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#define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc
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#define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc)
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#define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0
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#define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0)
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#define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4
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#define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4)
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#define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8
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#define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8)
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#define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc
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#define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc)
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#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0
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#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4
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#define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8
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#define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8)
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#define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc
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#define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc)
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#define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0
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#define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0)
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#define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4
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#define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4)
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#define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8
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#define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8)
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#define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec
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#define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)
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#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0
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#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4
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/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
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#define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
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#define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004
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#define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
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#define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
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#define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020)
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#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
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#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028)
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|
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/* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */
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#define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000
|
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#define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004
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#define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008
|
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#define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020
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#define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020)
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|
|
|
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|
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/* CM_CORE_AON.IPU_CM_CORE_AON register offsets */
|
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|
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#define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000
|
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|
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#define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004
|
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|
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#define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008
|
||
|
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#define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020
|
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|
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#define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
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#define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040
|
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|
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#define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050
|
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|
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#define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
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|
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#define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058
|
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|
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#define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
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||
|
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#define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060
|
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|
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#define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
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||
|
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#define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068
|
||
|
|
#define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
|
||
|
|
#define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070
|
||
|
|
#define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
|
||
|
|
#define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078
|
||
|
|
#define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
|
||
|
|
#define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080
|
||
|
|
#define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)
|
||
|
|
|
||
|
|
/* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */
|
||
|
|
#define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000
|
||
|
|
#define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004
|
||
|
|
#define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008
|
||
|
|
#define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020
|
||
|
|
#define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020)
|
||
|
|
|
||
|
|
/* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */
|
||
|
|
#define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000
|
||
|
|
#define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004
|
||
|
|
#define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020
|
||
|
|
#define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020)
|
||
|
|
|
||
|
|
/* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */
|
||
|
|
#define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000
|
||
|
|
#define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004
|
||
|
|
#define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020
|
||
|
|
#define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020)
|
||
|
|
|
||
|
|
/* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */
|
||
|
|
#define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000
|
||
|
|
#define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004
|
||
|
|
#define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020
|
||
|
|
#define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020)
|
||
|
|
|
||
|
|
/* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */
|
||
|
|
#define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000
|
||
|
|
#define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004
|
||
|
|
#define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020
|
||
|
|
#define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020)
|
||
|
|
|
||
|
|
/* CM_CORE_AON.RTC_CM_CORE_AON register offsets */
|
||
|
|
#define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000
|
||
|
|
#define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004
|
||
|
|
#define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004)
|
||
|
|
|
||
|
|
/* CM_CORE_AON.VPE_CM_CORE_AON register offsets */
|
||
|
|
#define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000
|
||
|
|
#define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004
|
||
|
|
#define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)
|
||
|
|
#define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008
|
||
|
|
|
||
|
|
#endif
|