403 lines
20 KiB
C
403 lines
20 KiB
C
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/*
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* Copyright (C) 2009 Nokia
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* Copyright (C) 2009 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU
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#define OMAP3_MUX(mode0, mux_value) \
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{ \
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.reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
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.value = (mux_value), \
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}
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/*
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* OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
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*
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* Extracted from the TRM. Add 0x48002030 to these values to get the
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* absolute addresses. The name in the macro is the mode-0 name of
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* the pin. NOTE: These registers are 16-bits wide.
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*
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* Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
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* of CHASSIS for some registers. For the defines, we follow the
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* 36XX naming, and use SDMMC and CHASSIS.
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*/
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#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000
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#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002
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#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004
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#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006
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#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008
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#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a
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#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c
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#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e
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#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010
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#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012
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#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014
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#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016
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#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018
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#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a
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#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c
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#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e
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#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020
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#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022
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#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024
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#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026
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#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028
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#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a
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#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c
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#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e
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#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030
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#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032
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#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034
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#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036
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#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
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#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a
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#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c
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#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e
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#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040
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#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042
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#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044
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#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046
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#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048
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#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
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#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c
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#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e
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#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050
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#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052
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#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054
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#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056
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#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058
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#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a
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#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c
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#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e
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#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060
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#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062
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#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064
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#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066
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#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068
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#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a
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#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c
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#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e
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#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070
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#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072
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#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074
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#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076
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#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078
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#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a
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#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c
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#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e
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#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080
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#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082
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#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084
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#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086
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#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088
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#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a
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#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c
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#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e
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#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090
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#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092
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#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094
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#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096
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#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098
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#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a
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#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c
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#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e
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#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0
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#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2
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#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4
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#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6
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#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8
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#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa
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#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac
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#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae
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#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0
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#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2
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#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4
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#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6
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#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8
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#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba
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#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc
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#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be
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#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0
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#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2
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#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4
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#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6
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#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8
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#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca
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#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc
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#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce
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#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0
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#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2
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#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4
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#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6
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#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8
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#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da
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#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc
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#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de
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#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0
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#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2
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#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4
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#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6
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#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8
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#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea
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#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec
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#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee
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#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0
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#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2
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#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4
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#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6
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#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8
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#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa
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#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc
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#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe
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#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100
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#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102
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#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104
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#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106
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#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108
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#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a
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#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c
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#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e
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#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110
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#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112
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#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114
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#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116
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#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118
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#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a
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#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c
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#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e
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/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
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#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120
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#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122
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#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124
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#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126
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#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128
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#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a
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#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c
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#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e
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#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130
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#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132
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#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134
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#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136
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#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138
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#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a
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#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c
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#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e
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#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140
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#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142
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#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144
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#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146
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#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148
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#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a
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#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c
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#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e
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#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150
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#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152
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#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154
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#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156
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#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158
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#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a
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#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c
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#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e
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#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160
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#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162
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#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164
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#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166
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#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168
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#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a
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#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c
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#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e
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#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170
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#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172
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#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174
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#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176
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#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178
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#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a
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#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c
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#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e
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#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180
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#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182
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#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184
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#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186
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#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188
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#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a
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#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c
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#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e
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#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190
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#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192
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#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194
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#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196
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#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198
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#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a
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#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c
|
||
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#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e
|
||
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#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0
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#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2
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#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4
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#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6
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#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8
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#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa
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#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac
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#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae
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#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0
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#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8
|
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2
|
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4
|
||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6
|
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8
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||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da
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||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc
|
||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de
|
||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0
|
||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2
|
||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4
|
||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6
|
||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8
|
||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea
|
||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec
|
||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee
|
||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0
|
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2
|
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6
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||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8
|
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa
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#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc
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||
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/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
|
||
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#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe
|
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#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200
|
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#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202
|
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#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204
|
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#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206
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#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208
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#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a
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#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c
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#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e
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#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210
|
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#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212
|
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#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214
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#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216
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#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218
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#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a
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#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c
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#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e
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#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220
|
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#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222
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#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224
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||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226
|
||
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#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228
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||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a
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||
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#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c
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||
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#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e
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||
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#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230
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||
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#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232
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||
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#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234
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||
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/* 36xx only */
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#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236
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#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570
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||
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#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572
|
||
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#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574
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||
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#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576
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||
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#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578
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||
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#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a
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||
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#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c
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||
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#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e
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||
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#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580
|
||
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#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582
|
||
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|
#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584
|
||
|
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#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588
|
||
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#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a
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||
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|
#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c
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||
|
|
#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e
|
||
|
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#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4
|
||
|
|
|
||
|
|
/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126
|
||
|
|
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8
|
||
|
|
#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca
|
||
|
|
#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0
|
||
|
|
#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea
|
||
|
|
#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec
|
||
|
|
#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee
|
||
|
|
#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0
|
||
|
|
#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2
|
||
|
|
#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4
|
||
|
|
#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6
|
||
|
|
#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c
|
||
|
|
#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e
|
||
|
|
#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20
|
||
|
|
#define OMAP3_CONTROL_PADCONF_GPIO_127 0xa24
|
||
|
|
#define OMAP3_CONTROL_PADCONF_GPIO_126 0xa26
|
||
|
|
#define OMAP3_CONTROL_PADCONF_GPIO_128 0xa28
|
||
|
|
#define OMAP3_CONTROL_PADCONF_GPIO_129 0xa2a
|
||
|
|
|
||
|
|
#define OMAP3_CONTROL_PADCONF_MUX_SIZE \
|
||
|
|
(OMAP3_CONTROL_PADCONF_GPIO_129 + 0x2)
|