132 lines
3.3 KiB
C
132 lines
3.3 KiB
C
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/*
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* arch/arm/mach-spear13xx/platsmp.c
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*
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* based upon linux/arch/arm/mach-realview/platsmp.c
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*
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* Copyright (C) 2012 ST Microelectronics Ltd.
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* Shiraz Hashim <shiraz.linux.kernel@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/jiffies.h>
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#include <linux/io.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_scu.h>
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#include <mach/spear.h>
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#include "generic.h"
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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sync_cache_w(&pen_release);
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}
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static DEFINE_SPINLOCK(boot_lock);
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static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
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static void spear13xx_secondary_init(unsigned int cpu)
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{
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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write_pen_release(cpu);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init spear13xx_smp_init_cpus(void)
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{
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unsigned int i, ncores = scu_get_core_count(scu_base);
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(scu_base);
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/*
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* Write the address of secondary startup into the system-wide location
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* (presently it is in SRAM). The BootMonitor waits until it receives a
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* soft interrupt, and then the secondary CPU branches to this address.
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*/
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__raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
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}
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const struct smp_operations spear13xx_smp_ops __initconst = {
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.smp_init_cpus = spear13xx_smp_init_cpus,
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.smp_prepare_cpus = spear13xx_smp_prepare_cpus,
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.smp_secondary_init = spear13xx_secondary_init,
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.smp_boot_secondary = spear13xx_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = spear13xx_cpu_die,
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#endif
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};
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