1303 lines
42 KiB
Plaintext
1303 lines
42 KiB
Plaintext
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "tegra210-p2530.dtsi"
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/ {
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model = "NVIDIA Tegra210 P2571 reference design";
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compatible = "nvidia,p2571", "nvidia,tegra210";
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pinmux: pinmux@700008d4 {
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pinctrl-names = "boot";
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pinctrl-0 = <&state_boot>;
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state_boot: pinmux {
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pex_l0_rst_n_pa0 {
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nvidia,pins = "pex_l0_rst_n_pa0";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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};
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pex_l0_clkreq_n_pa1 {
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nvidia,pins = "pex_l0_clkreq_n_pa1";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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};
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pex_wake_n_pa2 {
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nvidia,pins = "pex_wake_n_pa2";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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};
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pex_l1_rst_n_pa3 {
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nvidia,pins = "pex_l1_rst_n_pa3";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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};
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pex_l1_clkreq_n_pa4 {
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nvidia,pins = "pex_l1_clkreq_n_pa4";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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};
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sata_led_active_pa5 {
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nvidia,pins = "sata_led_active_pa5";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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pa6 {
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nvidia,pins = "pa6";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dap1_fs_pb0 {
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nvidia,pins = "dap1_fs_pb0";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dap1_din_pb1 {
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nvidia,pins = "dap1_din_pb1";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dap1_dout_pb2 {
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nvidia,pins = "dap1_dout_pb2";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dap1_sclk_pb3 {
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nvidia,pins = "dap1_sclk_pb3";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi2_mosi_pb4 {
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nvidia,pins = "spi2_mosi_pb4";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi2_miso_pb5 {
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nvidia,pins = "spi2_miso_pb5";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi2_sck_pb6 {
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nvidia,pins = "spi2_sck_pb6";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi2_cs0_pb7 {
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nvidia,pins = "spi2_cs0_pb7";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi1_mosi_pc0 {
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nvidia,pins = "spi1_mosi_pc0";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi1_miso_pc1 {
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nvidia,pins = "spi1_miso_pc1";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi1_sck_pc2 {
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nvidia,pins = "spi1_sck_pc2";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi1_cs0_pc3 {
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nvidia,pins = "spi1_cs0_pc3";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi1_cs1_pc4 {
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nvidia,pins = "spi1_cs1_pc4";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi4_sck_pc5 {
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nvidia,pins = "spi4_sck_pc5";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi4_cs0_pc6 {
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nvidia,pins = "spi4_cs0_pc6";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi4_mosi_pc7 {
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nvidia,pins = "spi4_mosi_pc7";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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spi4_miso_pd0 {
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nvidia,pins = "spi4_miso_pd0";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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uart3_tx_pd1 {
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nvidia,pins = "uart3_tx_pd1";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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uart3_rx_pd2 {
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nvidia,pins = "uart3_rx_pd2";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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uart3_rts_pd3 {
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nvidia,pins = "uart3_rts_pd3";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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uart3_cts_pd4 {
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nvidia,pins = "uart3_cts_pd4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dmic1_clk_pe0 {
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nvidia,pins = "dmic1_clk_pe0";
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nvidia,function = "i2s3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dmic1_dat_pe1 {
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nvidia,pins = "dmic1_dat_pe1";
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nvidia,function = "i2s3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dmic2_clk_pe2 {
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nvidia,pins = "dmic2_clk_pe2";
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nvidia,function = "i2s3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dmic2_dat_pe3 {
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nvidia,pins = "dmic2_dat_pe3";
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nvidia,function = "i2s3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dmic3_clk_pe4 {
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nvidia,pins = "dmic3_clk_pe4";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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dmic3_dat_pe5 {
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nvidia,pins = "dmic3_dat_pe5";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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pe6 {
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nvidia,pins = "pe6";
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nvidia,function = "rsvd0";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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pe7 {
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nvidia,pins = "pe7";
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nvidia,function = "pwm3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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};
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gen3_i2c_scl_pf0 {
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|
nvidia,pins = "gen3_i2c_scl_pf0";
|
||
|
|
nvidia,function = "i2c3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gen3_i2c_sda_pf1 {
|
||
|
|
nvidia,pins = "gen3_i2c_sda_pf1";
|
||
|
|
nvidia,function = "i2c3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart2_tx_pg0 {
|
||
|
|
nvidia,pins = "uart2_tx_pg0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart2_rx_pg1 {
|
||
|
|
nvidia,pins = "uart2_rx_pg1";
|
||
|
|
nvidia,function = "uartb";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart2_rts_pg2 {
|
||
|
|
nvidia,pins = "uart2_rts_pg2";
|
||
|
|
nvidia,function = "rsvd2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart2_cts_pg3 {
|
||
|
|
nvidia,pins = "uart2_cts_pg3";
|
||
|
|
nvidia,function = "rsvd2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
wifi_en_ph0 {
|
||
|
|
nvidia,pins = "wifi_en_ph0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
wifi_rst_ph1 {
|
||
|
|
nvidia,pins = "wifi_rst_ph1";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
wifi_wake_ap_ph2 {
|
||
|
|
nvidia,pins = "wifi_wake_ap_ph2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
ap_wake_bt_ph3 {
|
||
|
|
nvidia,pins = "ap_wake_bt_ph3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
bt_rst_ph4 {
|
||
|
|
nvidia,pins = "bt_rst_ph4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
bt_wake_ap_ph5 {
|
||
|
|
nvidia,pins = "bt_wake_ap_ph5";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
ph6 {
|
||
|
|
nvidia,pins = "ph6";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
ap_wake_nfc_ph7 {
|
||
|
|
nvidia,pins = "ap_wake_nfc_ph7";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
nfc_en_pi0 {
|
||
|
|
nvidia,pins = "nfc_en_pi0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
nfc_int_pi1 {
|
||
|
|
nvidia,pins = "nfc_int_pi1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gps_en_pi2 {
|
||
|
|
nvidia,pins = "gps_en_pi2";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gps_rst_pi3 {
|
||
|
|
nvidia,pins = "gps_rst_pi3";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart4_tx_pi4 {
|
||
|
|
nvidia,pins = "uart4_tx_pi4";
|
||
|
|
nvidia,function = "uartd";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart4_rx_pi5 {
|
||
|
|
nvidia,pins = "uart4_rx_pi5";
|
||
|
|
nvidia,function = "uartd";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart4_rts_pi6 {
|
||
|
|
nvidia,pins = "uart4_rts_pi6";
|
||
|
|
nvidia,function = "uartd";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart4_cts_pi7 {
|
||
|
|
nvidia,pins = "uart4_cts_pi7";
|
||
|
|
nvidia,function = "uartd";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gen1_i2c_sda_pj0 {
|
||
|
|
nvidia,pins = "gen1_i2c_sda_pj0";
|
||
|
|
nvidia,function = "i2c1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gen1_i2c_scl_pj1 {
|
||
|
|
nvidia,pins = "gen1_i2c_scl_pj1";
|
||
|
|
nvidia,function = "i2c1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gen2_i2c_scl_pj2 {
|
||
|
|
nvidia,pins = "gen2_i2c_scl_pj2";
|
||
|
|
nvidia,function = "i2c2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
gen2_i2c_sda_pj3 {
|
||
|
|
nvidia,pins = "gen2_i2c_sda_pj3";
|
||
|
|
nvidia,function = "i2c2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
dap4_fs_pj4 {
|
||
|
|
nvidia,pins = "dap4_fs_pj4";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap4_din_pj5 {
|
||
|
|
nvidia,pins = "dap4_din_pj5";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap4_dout_pj6 {
|
||
|
|
nvidia,pins = "dap4_dout_pj6";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap4_sclk_pj7 {
|
||
|
|
nvidia,pins = "dap4_sclk_pj7";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk0 {
|
||
|
|
nvidia,pins = "pk0";
|
||
|
|
nvidia,function = "rsvd2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk1 {
|
||
|
|
nvidia,pins = "pk1";
|
||
|
|
nvidia,function = "rsvd2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk2 {
|
||
|
|
nvidia,pins = "pk2";
|
||
|
|
nvidia,function = "rsvd2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk3 {
|
||
|
|
nvidia,pins = "pk3";
|
||
|
|
nvidia,function = "rsvd2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk4 {
|
||
|
|
nvidia,pins = "pk4";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk5 {
|
||
|
|
nvidia,pins = "pk5";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk6 {
|
||
|
|
nvidia,pins = "pk6";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk7 {
|
||
|
|
nvidia,pins = "pk7";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pl0 {
|
||
|
|
nvidia,pins = "pl0";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pl1 {
|
||
|
|
nvidia,pins = "pl1";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc1_clk_pm0 {
|
||
|
|
nvidia,pins = "sdmmc1_clk_pm0";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc1_cmd_pm1 {
|
||
|
|
nvidia,pins = "sdmmc1_cmd_pm1";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc1_dat3_pm2 {
|
||
|
|
nvidia,pins = "sdmmc1_dat3_pm2";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc1_dat2_pm3 {
|
||
|
|
nvidia,pins = "sdmmc1_dat2_pm3";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc1_dat1_pm4 {
|
||
|
|
nvidia,pins = "sdmmc1_dat1_pm4";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc1_dat0_pm5 {
|
||
|
|
nvidia,pins = "sdmmc1_dat0_pm5";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc3_clk_pp0 {
|
||
|
|
nvidia,pins = "sdmmc3_clk_pp0";
|
||
|
|
nvidia,function = "sdmmc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc3_cmd_pp1 {
|
||
|
|
nvidia,pins = "sdmmc3_cmd_pp1";
|
||
|
|
nvidia,function = "sdmmc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc3_dat3_pp2 {
|
||
|
|
nvidia,pins = "sdmmc3_dat3_pp2";
|
||
|
|
nvidia,function = "sdmmc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc3_dat2_pp3 {
|
||
|
|
nvidia,pins = "sdmmc3_dat2_pp3";
|
||
|
|
nvidia,function = "sdmmc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc3_dat1_pp4 {
|
||
|
|
nvidia,pins = "sdmmc3_dat1_pp4";
|
||
|
|
nvidia,function = "sdmmc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc3_dat0_pp5 {
|
||
|
|
nvidia,pins = "sdmmc3_dat0_pp5";
|
||
|
|
nvidia,function = "sdmmc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam1_mclk_ps0 {
|
||
|
|
nvidia,pins = "cam1_mclk_ps0";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam2_mclk_ps1 {
|
||
|
|
nvidia,pins = "cam2_mclk_ps1";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam_i2c_scl_ps2 {
|
||
|
|
nvidia,pins = "cam_i2c_scl_ps2";
|
||
|
|
nvidia,function = "i2cvi";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam_i2c_sda_ps3 {
|
||
|
|
nvidia,pins = "cam_i2c_sda_ps3";
|
||
|
|
nvidia,function = "i2cvi";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam_rst_ps4 {
|
||
|
|
nvidia,pins = "cam_rst_ps4";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam_af_en_ps5 {
|
||
|
|
nvidia,pins = "cam_af_en_ps5";
|
||
|
|
nvidia,function = "rsvd2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam_flash_en_ps6 {
|
||
|
|
nvidia,pins = "cam_flash_en_ps6";
|
||
|
|
nvidia,function = "rsvd2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam1_pwdn_ps7 {
|
||
|
|
nvidia,pins = "cam1_pwdn_ps7";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam2_pwdn_pt0 {
|
||
|
|
nvidia,pins = "cam2_pwdn_pt0";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam1_strobe_pt1 {
|
||
|
|
nvidia,pins = "cam1_strobe_pt1";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart1_tx_pu0 {
|
||
|
|
nvidia,pins = "uart1_tx_pu0";
|
||
|
|
nvidia,function = "uarta";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart1_rx_pu1 {
|
||
|
|
nvidia,pins = "uart1_rx_pu1";
|
||
|
|
nvidia,function = "uarta";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart1_rts_pu2 {
|
||
|
|
nvidia,pins = "uart1_rts_pu2";
|
||
|
|
nvidia,function = "uarta";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart1_cts_pu3 {
|
||
|
|
nvidia,pins = "uart1_cts_pu3";
|
||
|
|
nvidia,function = "uarta";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
lcd_bl_pwm_pv0 {
|
||
|
|
nvidia,pins = "lcd_bl_pwm_pv0";
|
||
|
|
nvidia,function = "pwm0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
lcd_bl_en_pv1 {
|
||
|
|
nvidia,pins = "lcd_bl_en_pv1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
lcd_rst_pv2 {
|
||
|
|
nvidia,pins = "lcd_rst_pv2";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
lcd_gpio1_pv3 {
|
||
|
|
nvidia,pins = "lcd_gpio1_pv3";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
lcd_gpio2_pv4 {
|
||
|
|
nvidia,pins = "lcd_gpio2_pv4";
|
||
|
|
nvidia,function = "pwm1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
ap_ready_pv5 {
|
||
|
|
nvidia,pins = "ap_ready_pv5";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
touch_rst_pv6 {
|
||
|
|
nvidia,pins = "touch_rst_pv6";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
touch_clk_pv7 {
|
||
|
|
nvidia,pins = "touch_clk_pv7";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
modem_wake_ap_px0 {
|
||
|
|
nvidia,pins = "modem_wake_ap_px0";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
touch_int_px1 {
|
||
|
|
nvidia,pins = "touch_int_px1";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
motion_int_px2 {
|
||
|
|
nvidia,pins = "motion_int_px2";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
als_prox_int_px3 {
|
||
|
|
nvidia,pins = "als_prox_int_px3";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
temp_alert_px4 {
|
||
|
|
nvidia,pins = "temp_alert_px4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
button_power_on_px5 {
|
||
|
|
nvidia,pins = "button_power_on_px5";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
button_vol_up_px6 {
|
||
|
|
nvidia,pins = "button_vol_up_px6";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
button_vol_down_px7 {
|
||
|
|
nvidia,pins = "button_vol_down_px7";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
button_slide_sw_py0 {
|
||
|
|
nvidia,pins = "button_slide_sw_py0";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
button_home_py1 {
|
||
|
|
nvidia,pins = "button_home_py1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
lcd_te_py2 {
|
||
|
|
nvidia,pins = "lcd_te_py2";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pwr_i2c_scl_py3 {
|
||
|
|
nvidia,pins = "pwr_i2c_scl_py3";
|
||
|
|
nvidia,function = "i2cpmu";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pwr_i2c_sda_py4 {
|
||
|
|
nvidia,pins = "pwr_i2c_sda_py4";
|
||
|
|
nvidia,function = "i2cpmu";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
clk_32k_out_py5 {
|
||
|
|
nvidia,pins = "clk_32k_out_py5";
|
||
|
|
nvidia,function = "soc";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pz0 {
|
||
|
|
nvidia,pins = "pz0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pz1 {
|
||
|
|
nvidia,pins = "pz1";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pz2 {
|
||
|
|
nvidia,pins = "pz2";
|
||
|
|
nvidia,function = "rsvd2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pz3 {
|
||
|
|
nvidia,pins = "pz3";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pz4 {
|
||
|
|
nvidia,pins = "pz4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pz5 {
|
||
|
|
nvidia,pins = "pz5";
|
||
|
|
nvidia,function = "soc";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap2_fs_paa0 {
|
||
|
|
nvidia,pins = "dap2_fs_paa0";
|
||
|
|
nvidia,function = "i2s2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap2_sclk_paa1 {
|
||
|
|
nvidia,pins = "dap2_sclk_paa1";
|
||
|
|
nvidia,function = "i2s2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap2_din_paa2 {
|
||
|
|
nvidia,pins = "dap2_din_paa2";
|
||
|
|
nvidia,function = "i2s2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap2_dout_paa3 {
|
||
|
|
nvidia,pins = "dap2_dout_paa3";
|
||
|
|
nvidia,function = "i2s2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
aud_mclk_pbb0 {
|
||
|
|
nvidia,pins = "aud_mclk_pbb0";
|
||
|
|
nvidia,function = "aud";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dvfs_pwm_pbb1 {
|
||
|
|
nvidia,pins = "dvfs_pwm_pbb1";
|
||
|
|
nvidia,function = "cldvfs";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dvfs_clk_pbb2 {
|
||
|
|
nvidia,pins = "dvfs_clk_pbb2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gpio_x1_aud_pbb3 {
|
||
|
|
nvidia,pins = "gpio_x1_aud_pbb3";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gpio_x3_aud_pbb4 {
|
||
|
|
nvidia,pins = "gpio_x3_aud_pbb4";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
hdmi_cec_pcc0 {
|
||
|
|
nvidia,pins = "hdmi_cec_pcc0";
|
||
|
|
nvidia,function = "cec";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
hdmi_int_dp_hpd_pcc1 {
|
||
|
|
nvidia,pins = "hdmi_int_dp_hpd_pcc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spdif_out_pcc2 {
|
||
|
|
nvidia,pins = "spdif_out_pcc2";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spdif_in_pcc3 {
|
||
|
|
nvidia,pins = "spdif_in_pcc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
usb_vbus_en0_pcc4 {
|
||
|
|
nvidia,pins = "usb_vbus_en0_pcc4";
|
||
|
|
nvidia,function = "usb";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
usb_vbus_en1_pcc5 {
|
||
|
|
nvidia,pins = "usb_vbus_en1_pcc5";
|
||
|
|
nvidia,function = "usb";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
dp_hpd0_pcc6 {
|
||
|
|
nvidia,pins = "dp_hpd0_pcc6";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pcc7 {
|
||
|
|
nvidia,pins = "pcc7";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi2_cs1_pdd0 {
|
||
|
|
nvidia,pins = "spi2_cs1_pdd0";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
qspi_sck_pee0 {
|
||
|
|
nvidia,pins = "qspi_sck_pee0";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
qspi_cs_n_pee1 {
|
||
|
|
nvidia,pins = "qspi_cs_n_pee1";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
qspi_io0_pee2 {
|
||
|
|
nvidia,pins = "qspi_io0_pee2";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
qspi_io1_pee3 {
|
||
|
|
nvidia,pins = "qspi_io1_pee3";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
qspi_io2_pee4 {
|
||
|
|
nvidia,pins = "qspi_io2_pee4";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
qspi_io3_pee5 {
|
||
|
|
nvidia,pins = "qspi_io3_pee5";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
core_pwr_req {
|
||
|
|
nvidia,pins = "core_pwr_req";
|
||
|
|
nvidia,function = "core";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cpu_pwr_req {
|
||
|
|
nvidia,pins = "cpu_pwr_req";
|
||
|
|
nvidia,function = "cpu";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pwr_int_n {
|
||
|
|
nvidia,pins = "pwr_int_n";
|
||
|
|
nvidia,function = "pmi";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
clk_32k_in {
|
||
|
|
nvidia,pins = "clk_32k_in";
|
||
|
|
nvidia,function = "clk";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
jtag_rtck {
|
||
|
|
nvidia,pins = "jtag_rtck";
|
||
|
|
nvidia,function = "jtag";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
clk_req {
|
||
|
|
nvidia,pins = "clk_req";
|
||
|
|
nvidia,function = "sys";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
shutdown {
|
||
|
|
nvidia,pins = "shutdown";
|
||
|
|
nvidia,function = "shutdown";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|