378 lines
8.9 KiB
Plaintext
378 lines
8.9 KiB
Plaintext
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/*
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* dts file for Xilinx ZynqMP
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*
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* (C) Copyright 2014 - 2015, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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/ {
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compatible = "xlnx,zynqmp";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x3>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupt-parent = <&gic>;
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interrupts = <0 143 4>,
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<0 144 4>,
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<0 145 4>,
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<0 146 4>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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amba_apu: amba_apu@0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0 0 0xffffffff>;
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gic: interrupt-controller@f9010000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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reg = <0x0 0xf9010000 0x10000>,
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<0x0 0xf9020000 0x20000>,
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<0x0 0xf9040000 0x20000>,
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<0x0 0xf9060000 0x20000>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <1 9 0xf04>;
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};
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};
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amba: amba {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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can0: can@ff060000 {
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compatible = "xlnx,zynq-can-1.0";
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status = "disabled";
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clock-names = "can_clk", "pclk";
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reg = <0x0 0xff060000 0x0 0x1000>;
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interrupts = <0 23 4>;
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interrupt-parent = <&gic>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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};
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can1: can@ff070000 {
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compatible = "xlnx,zynq-can-1.0";
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status = "disabled";
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clock-names = "can_clk", "pclk";
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reg = <0x0 0xff070000 0x0 0x1000>;
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interrupts = <0 24 4>;
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interrupt-parent = <&gic>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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};
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gem0: ethernet@ff0b0000 {
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compatible = "cdns,gem";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 57 4>, <0 57 4>;
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reg = <0x0 0xff0b0000 0x0 0x1000>;
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clock-names = "pclk", "hclk", "tx_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gem1: ethernet@ff0c0000 {
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compatible = "cdns,gem";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 59 4>, <0 59 4>;
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reg = <0x0 0xff0c0000 0x0 0x1000>;
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clock-names = "pclk", "hclk", "tx_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gem2: ethernet@ff0d0000 {
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compatible = "cdns,gem";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 61 4>, <0 61 4>;
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reg = <0x0 0xff0d0000 0x0 0x1000>;
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clock-names = "pclk", "hclk", "tx_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gem3: ethernet@ff0e0000 {
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compatible = "cdns,gem";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 63 4>, <0 63 4>;
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reg = <0x0 0xff0e0000 0x0 0x1000>;
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clock-names = "pclk", "hclk", "tx_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gpio: gpio@ff0a0000 {
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compatible = "xlnx,zynqmp-gpio-1.0";
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status = "disabled";
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#gpio-cells = <0x2>;
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interrupt-parent = <&gic>;
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interrupts = <0 16 4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0xff0a0000 0x0 0x1000>;
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};
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i2c0: i2c@ff020000 {
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compatible = "cdns,i2c-r1p14";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 17 4>;
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reg = <0x0 0xff020000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c1: i2c@ff030000 {
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compatible = "cdns,i2c-r1p14";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 18 4>;
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reg = <0x0 0xff030000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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pcie: pcie@fd0e0000 {
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compatible = "xlnx,nwl-pcie-2.11";
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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msi-controller;
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device_type = "pci";
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interrupt-parent = <&gic>;
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interrupts = <0 118 4>,
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<0 117 4>,
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<0 116 4>,
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<0 115 4>, /* MSI_1 [63...32] */
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<0 114 4>; /* MSI_0 [31...0] */
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interrupt-names = "misc", "dummy", "intx",
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"msi1", "msi0";
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msi-parent = <&pcie>;
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reg = <0x0 0xfd0e0000 0x0 0x1000>,
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<0x0 0xfd480000 0x0 0x1000>,
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<0x80 0x00000000 0x0 0x1000000>;
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reg-names = "breg", "pcireg", "cfg";
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ranges = <0x02000000 0x00000000 0xe0000000 0x00000000
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0xe0000000 0x00000000 0x10000000
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/* non-prefetchable memory */
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0x43000000 0x00000006 0x00000000 0x00000006
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0x00000000 0x00000002 0x00000000>;
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/* prefetchable memory */
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
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<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
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<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
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<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
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pcie_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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sata: ahci@fd0c0000 {
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compatible = "ceva,ahci-1v84";
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status = "disabled";
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reg = <0x0 0xfd0c0000 0x0 0x2000>;
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interrupt-parent = <&gic>;
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interrupts = <0 133 4>;
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};
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sdhci0: sdhci@ff160000 {
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 48 4>;
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reg = <0x0 0xff160000 0x0 0x1000>;
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clock-names = "clk_xin", "clk_ahb";
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};
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sdhci1: sdhci@ff170000 {
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 49 4>;
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reg = <0x0 0xff170000 0x0 0x1000>;
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clock-names = "clk_xin", "clk_ahb";
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};
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smmu: smmu@fd800000 {
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compatible = "arm,mmu-500";
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reg = <0x0 0xfd800000 0x0 0x20000>;
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#global-interrupts = <1>;
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interrupt-parent = <&gic>;
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interrupts = <0 157 4>,
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<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
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<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
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<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
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<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
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};
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spi0: spi@ff040000 {
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compatible = "cdns,spi-r1p6";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 19 4>;
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reg = <0x0 0xff040000 0x0 0x1000>;
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clock-names = "ref_clk", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@ff050000 {
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compatible = "cdns,spi-r1p6";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 20 4>;
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reg = <0x0 0xff050000 0x0 0x1000>;
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clock-names = "ref_clk", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ttc0: timer@ff110000 {
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compatible = "cdns,ttc";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
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reg = <0x0 0xff110000 0x0 0x1000>;
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timer-width = <32>;
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};
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ttc1: timer@ff120000 {
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compatible = "cdns,ttc";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
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reg = <0x0 0xff120000 0x0 0x1000>;
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timer-width = <32>;
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};
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ttc2: timer@ff130000 {
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compatible = "cdns,ttc";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
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reg = <0x0 0xff130000 0x0 0x1000>;
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timer-width = <32>;
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};
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ttc3: timer@ff140000 {
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compatible = "cdns,ttc";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
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reg = <0x0 0xff140000 0x0 0x1000>;
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timer-width = <32>;
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};
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uart0: serial@ff000000 {
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compatible = "cdns,uart-r1p8";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 21 4>;
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reg = <0x0 0xff000000 0x0 0x1000>;
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clock-names = "uart_clk", "pclk";
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};
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uart1: serial@ff010000 {
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compatible = "cdns,uart-r1p8";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 22 4>;
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reg = <0x0 0xff010000 0x0 0x1000>;
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clock-names = "uart_clk", "pclk";
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};
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usb0: usb@fe200000 {
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compatible = "snps,dwc3";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 65 4>;
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reg = <0x0 0xfe200000 0x0 0x40000>;
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clock-names = "clk_xin", "clk_ahb";
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};
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usb1: usb@fe300000 {
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compatible = "snps,dwc3";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 70 4>;
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reg = <0x0 0xfe300000 0x0 0x40000>;
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clock-names = "clk_xin", "clk_ahb";
|
||
|
|
};
|
||
|
|
|
||
|
|
watchdog0: watchdog@fd4d0000 {
|
||
|
|
compatible = "cdns,wdt-r1p2";
|
||
|
|
status = "disabled";
|
||
|
|
interrupt-parent = <&gic>;
|
||
|
|
interrupts = <0 113 1>;
|
||
|
|
reg = <0x0 0xfd4d0000 0x0 0x1000>;
|
||
|
|
timeout-sec = <10>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|