421 lines
12 KiB
C
421 lines
12 KiB
C
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ARM64_KVM_MMU_H__
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#define __ARM64_KVM_MMU_H__
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#include <asm/page.h>
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#include <asm/memory.h>
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#include <asm/cpufeature.h>
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/*
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* As ARMv8.0 only has the TTBR0_EL2 register, we cannot express
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* "negative" addresses. This makes it impossible to directly share
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* mappings with the kernel.
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*
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* Instead, give the HYP mode its own VA region at a fixed offset from
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* the kernel by just masking the top bits (which are all ones for a
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* kernel address). We need to find out how many bits to mask.
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*
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* We want to build a set of page tables that cover both parts of the
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* idmap (the trampoline page used to initialize EL2), and our normal
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* runtime VA space, at the same time.
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*
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* Given that the kernel uses VA_BITS for its entire address space,
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* and that half of that space (VA_BITS - 1) is used for the linear
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* mapping, we can also limit the EL2 space to (VA_BITS - 1).
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*
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* The main question is "Within the VA_BITS space, does EL2 use the
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* top or the bottom half of that space to shadow the kernel's linear
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* mapping?". As we need to idmap the trampoline page, this is
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* determined by the range in which this page lives.
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*
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* If the page is in the bottom half, we have to use the top half. If
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* the page is in the top half, we have to use the bottom half:
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*
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* T = __pa_symbol(__hyp_idmap_text_start)
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* if (T & BIT(VA_BITS - 1))
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* HYP_VA_MIN = 0 //idmap in upper half
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* else
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* HYP_VA_MIN = 1 << (VA_BITS - 1)
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* HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1
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*
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* This of course assumes that the trampoline page exists within the
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* VA_BITS range. If it doesn't, then it means we're in the odd case
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* where the kernel idmap (as well as HYP) uses more levels than the
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* kernel runtime page tables (as seen when the kernel is configured
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* for 4k pages, 39bits VA, and yet memory lives just above that
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* limit, forcing the idmap to use 4 levels of page tables while the
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* kernel itself only uses 3). In this particular case, it doesn't
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* matter which side of VA_BITS we use, as we're guaranteed not to
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* conflict with anything.
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*
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* When using VHE, there are no separate hyp mappings and all KVM
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* functionality is already mapped as part of the main kernel
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* mappings, and none of this applies in that case.
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*/
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#define HYP_PAGE_OFFSET_HIGH_MASK ((UL(1) << VA_BITS) - 1)
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#define HYP_PAGE_OFFSET_LOW_MASK ((UL(1) << (VA_BITS - 1)) - 1)
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#ifdef __ASSEMBLY__
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#include <asm/alternative.h>
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#include <asm/cpufeature.h>
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/*
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* Convert a kernel VA into a HYP VA.
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* reg: VA to be converted.
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*
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* This generates the following sequences:
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* - High mask:
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* and x0, x0, #HYP_PAGE_OFFSET_HIGH_MASK
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* nop
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* - Low mask:
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* and x0, x0, #HYP_PAGE_OFFSET_HIGH_MASK
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* and x0, x0, #HYP_PAGE_OFFSET_LOW_MASK
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* - VHE:
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* nop
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* nop
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*
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* The "low mask" version works because the mask is a strict subset of
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* the "high mask", hence performing the first mask for nothing.
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* Should be completely invisible on any viable CPU.
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*/
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.macro kern_hyp_va reg
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alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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and \reg, \reg, #HYP_PAGE_OFFSET_HIGH_MASK
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alternative_else_nop_endif
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alternative_if ARM64_HYP_OFFSET_LOW
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and \reg, \reg, #HYP_PAGE_OFFSET_LOW_MASK
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alternative_else_nop_endif
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.endm
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#else
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#include <asm/pgalloc.h>
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#include <asm/cachetype.h>
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#include <asm/cacheflush.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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static inline unsigned long __kern_hyp_va(unsigned long v)
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{
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asm volatile(ALTERNATIVE("and %0, %0, %1",
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"nop",
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ARM64_HAS_VIRT_HOST_EXTN)
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: "+r" (v)
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: "i" (HYP_PAGE_OFFSET_HIGH_MASK));
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asm volatile(ALTERNATIVE("nop",
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"and %0, %0, %1",
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ARM64_HYP_OFFSET_LOW)
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: "+r" (v)
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: "i" (HYP_PAGE_OFFSET_LOW_MASK));
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return v;
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}
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#define kern_hyp_va(v) ((typeof(v))(__kern_hyp_va((unsigned long)(v))))
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/*
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* Obtain the PC-relative address of a kernel symbol
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* s: symbol
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*
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* The goal of this macro is to return a symbol's address based on a
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* PC-relative computation, as opposed to a loading the VA from a
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* constant pool or something similar. This works well for HYP, as an
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* absolute VA is guaranteed to be wrong. Only use this if trying to
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* obtain the address of a symbol (i.e. not something you obtained by
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* following a pointer).
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*/
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#define hyp_symbol_addr(s) \
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({ \
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typeof(s) *addr; \
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asm("adrp %0, %1\n" \
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"add %0, %0, :lo12:%1\n" \
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: "=r" (addr) : "S" (&s)); \
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addr; \
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})
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/*
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* We currently only support a 40bit IPA.
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*/
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#define KVM_PHYS_SHIFT (40)
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#define KVM_PHYS_SIZE (1UL << KVM_PHYS_SHIFT)
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#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1UL)
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#include <asm/stage2_pgtable.h>
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int create_hyp_mappings(void *from, void *to, pgprot_t prot);
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int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
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void free_hyp_pgds(void);
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void stage2_unmap_vm(struct kvm *kvm);
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int kvm_alloc_stage2_pgd(struct kvm *kvm);
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void kvm_free_stage2_pgd(struct kvm *kvm);
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int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
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phys_addr_t pa, unsigned long size, bool writable);
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int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
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void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
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phys_addr_t kvm_mmu_get_httbr(void);
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phys_addr_t kvm_get_idmap_vector(void);
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phys_addr_t kvm_get_idmap_start(void);
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int kvm_mmu_init(void);
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void kvm_clear_hyp_idmap(void);
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#define kvm_set_pte(ptep, pte) set_pte(ptep, pte)
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#define kvm_set_pmd(pmdp, pmd) set_pmd(pmdp, pmd)
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static inline pte_t kvm_s2pte_mkwrite(pte_t pte)
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{
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pte_val(pte) |= PTE_S2_RDWR;
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return pte;
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}
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static inline pmd_t kvm_s2pmd_mkwrite(pmd_t pmd)
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{
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pmd_val(pmd) |= PMD_S2_RDWR;
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return pmd;
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}
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static inline void kvm_set_s2pte_readonly(pte_t *pte)
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{
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pteval_t pteval;
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unsigned long tmp;
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asm volatile("// kvm_set_s2pte_readonly\n"
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" prfm pstl1strm, %2\n"
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"1: ldxr %0, %2\n"
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" and %0, %0, %3 // clear PTE_S2_RDWR\n"
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" orr %0, %0, %4 // set PTE_S2_RDONLY\n"
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" stxr %w1, %0, %2\n"
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" cbnz %w1, 1b\n"
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: "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*pte))
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: "L" (~PTE_S2_RDWR), "L" (PTE_S2_RDONLY));
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}
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static inline bool kvm_s2pte_readonly(pte_t *pte)
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{
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return (pte_val(*pte) & PTE_S2_RDWR) == PTE_S2_RDONLY;
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}
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static inline void kvm_set_s2pmd_readonly(pmd_t *pmd)
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{
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kvm_set_s2pte_readonly((pte_t *)pmd);
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}
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static inline bool kvm_s2pmd_readonly(pmd_t *pmd)
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{
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return kvm_s2pte_readonly((pte_t *)pmd);
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}
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static inline bool kvm_page_empty(void *ptr)
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{
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struct page *ptr_page = virt_to_page(ptr);
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return page_count(ptr_page) == 1;
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}
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#define hyp_pte_table_empty(ptep) kvm_page_empty(ptep)
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#ifdef __PAGETABLE_PMD_FOLDED
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#define hyp_pmd_table_empty(pmdp) (0)
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#else
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#define hyp_pmd_table_empty(pmdp) kvm_page_empty(pmdp)
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#endif
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#ifdef __PAGETABLE_PUD_FOLDED
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#define hyp_pud_table_empty(pudp) (0)
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#else
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#define hyp_pud_table_empty(pudp) kvm_page_empty(pudp)
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#endif
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struct kvm;
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#define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
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static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
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{
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return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
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}
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static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu,
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kvm_pfn_t pfn,
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unsigned long size,
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bool ipa_uncached)
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{
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void *va = page_address(pfn_to_page(pfn));
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kvm_flush_dcache_to_poc(va, size);
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if (!icache_is_aliasing()) { /* PIPT */
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flush_icache_range((unsigned long)va,
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(unsigned long)va + size);
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} else if (!icache_is_aivivt()) { /* non ASID-tagged VIVT */
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/* any kind of VIPT cache */
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__flush_icache_all();
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}
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}
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static inline void __kvm_flush_dcache_pte(pte_t pte)
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{
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struct page *page = pte_page(pte);
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kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
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}
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static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
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{
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struct page *page = pmd_page(pmd);
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kvm_flush_dcache_to_poc(page_address(page), PMD_SIZE);
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}
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static inline void __kvm_flush_dcache_pud(pud_t pud)
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{
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struct page *page = pud_page(pud);
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kvm_flush_dcache_to_poc(page_address(page), PUD_SIZE);
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}
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#define kvm_virt_to_phys(x) __pa_symbol(x)
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void kvm_set_way_flush(struct kvm_vcpu *vcpu);
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void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
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static inline bool __kvm_cpu_uses_extended_idmap(void)
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{
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return __cpu_uses_extended_idmap();
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}
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/*
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* Can't use pgd_populate here, because the extended idmap adds an extra level
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* above CONFIG_PGTABLE_LEVELS (which is 2 or 3 if we're using the extended
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* idmap), and pgd_populate is only available if CONFIG_PGTABLE_LEVELS = 4.
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*/
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static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd,
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pgd_t *hyp_pgd,
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pgd_t *merged_hyp_pgd,
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unsigned long hyp_idmap_start)
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{
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int idmap_idx;
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/*
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* Use the first entry to access the HYP mappings. It is
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* guaranteed to be free, otherwise we wouldn't use an
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* extended idmap.
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*/
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VM_BUG_ON(pgd_val(merged_hyp_pgd[0]));
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merged_hyp_pgd[0] = __pgd(__pa(hyp_pgd) | PMD_TYPE_TABLE);
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/*
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* Create another extended level entry that points to the boot HYP map,
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* which contains an ID mapping of the HYP init code. We essentially
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* merge the boot and runtime HYP maps by doing so, but they don't
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* overlap anyway, so this is fine.
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*/
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idmap_idx = hyp_idmap_start >> VA_BITS;
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VM_BUG_ON(pgd_val(merged_hyp_pgd[idmap_idx]));
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merged_hyp_pgd[idmap_idx] = __pgd(__pa(boot_hyp_pgd) | PMD_TYPE_TABLE);
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}
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static inline unsigned int kvm_get_vmid_bits(void)
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{
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int reg = read_system_reg(SYS_ID_AA64MMFR1_EL1);
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return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8;
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}
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/*
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* We are not in the kvm->srcu critical section most of the time, so we take
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||
|
|
* the SRCU read lock here. Since we copy the data from the user page, we
|
||
|
|
* can immediately drop the lock again.
|
||
|
|
*/
|
||
|
|
static inline int kvm_read_guest_lock(struct kvm *kvm,
|
||
|
|
gpa_t gpa, void *data, unsigned long len)
|
||
|
|
{
|
||
|
|
int srcu_idx = srcu_read_lock(&kvm->srcu);
|
||
|
|
int ret = kvm_read_guest(kvm, gpa, data, len);
|
||
|
|
|
||
|
|
srcu_read_unlock(&kvm->srcu, srcu_idx);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
|
||
|
|
#include <asm/mmu.h>
|
||
|
|
|
||
|
|
static inline void *kvm_get_hyp_vector(void)
|
||
|
|
{
|
||
|
|
struct bp_hardening_data *data = arm64_get_bp_hardening_data();
|
||
|
|
void *vect = kvm_ksym_ref(__kvm_hyp_vector);
|
||
|
|
|
||
|
|
if (data->fn) {
|
||
|
|
vect = __bp_harden_hyp_vecs_start +
|
||
|
|
data->hyp_vectors_slot * SZ_2K;
|
||
|
|
|
||
|
|
if (!cpus_have_const_cap(ARM64_HAS_VIRT_HOST_EXTN))
|
||
|
|
vect = lm_alias(vect);
|
||
|
|
}
|
||
|
|
|
||
|
|
return vect;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int kvm_map_vectors(void)
|
||
|
|
{
|
||
|
|
return create_hyp_mappings(kvm_ksym_ref(__bp_harden_hyp_vecs_start),
|
||
|
|
kvm_ksym_ref(__bp_harden_hyp_vecs_end),
|
||
|
|
PAGE_HYP_EXEC);
|
||
|
|
}
|
||
|
|
|
||
|
|
#else
|
||
|
|
static inline void *kvm_get_hyp_vector(void)
|
||
|
|
{
|
||
|
|
return kvm_ksym_ref(__kvm_hyp_vector);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int kvm_map_vectors(void)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_ARM64_SSBD
|
||
|
|
DECLARE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
|
||
|
|
|
||
|
|
static inline int hyp_map_aux_data(void)
|
||
|
|
{
|
||
|
|
int cpu, err;
|
||
|
|
|
||
|
|
for_each_possible_cpu(cpu) {
|
||
|
|
u64 *ptr;
|
||
|
|
|
||
|
|
ptr = per_cpu_ptr(&arm64_ssbd_callback_required, cpu);
|
||
|
|
err = create_hyp_mappings(ptr, ptr + 1, PAGE_HYP);
|
||
|
|
if (err)
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
static inline int hyp_map_aux_data(void)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __ASSEMBLY__ */
|
||
|
|
#endif /* __ARM64_KVM_MMU_H__ */
|