842 lines
18 KiB
C
842 lines
18 KiB
C
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/*
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* Copyright 2004-2009 Analog Devices Inc.
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* 2005 National ICT Australia (NICTA)
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* Aidan Williams <aidan@nicta.com.au>
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/device.h>
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#include <linux/export.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/i2c.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/dma.h>
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#include <asm/bfin5xx_spi.h>
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#include <asm/reboot.h>
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#include <asm/portmux.h>
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#include <asm/dpmc.h>
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#include <asm/bfin_sdh.h>
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#include <linux/spi/ad7877.h>
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#include <net/dsa.h>
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/*
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* Name the Board for the /proc/cpuinfo
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*/
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const char bfin_board_name[] = "ADI BF518F-EZBRD";
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/*
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* Driver needs to know address, irq and flag pin.
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*/
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#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
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static struct mtd_partition ezbrd_partitions[] = {
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{
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.name = "bootloader(nor)",
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.size = 0x40000,
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.offset = 0,
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}, {
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.name = "linux kernel(nor)",
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.size = 0x1C0000,
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.offset = MTDPART_OFS_APPEND,
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}, {
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.name = "file system(nor)",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_APPEND,
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}
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};
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static struct physmap_flash_data ezbrd_flash_data = {
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.width = 2,
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.parts = ezbrd_partitions,
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.nr_parts = ARRAY_SIZE(ezbrd_partitions),
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};
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static struct resource ezbrd_flash_resource = {
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.start = 0x20000000,
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#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
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.end = 0x202fffff,
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#else
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.end = 0x203fffff,
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#endif
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device ezbrd_flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &ezbrd_flash_data,
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},
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.num_resources = 1,
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.resource = &ezbrd_flash_resource,
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};
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#endif
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#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
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static struct platform_device rtc_device = {
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.name = "rtc-bfin",
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.id = -1,
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};
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#endif
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#if IS_ENABLED(CONFIG_BFIN_MAC)
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#include <linux/bfin_mac.h>
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static const unsigned short bfin_mac_peripherals[] = {
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P_MII0_ETxD0,
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P_MII0_ETxD1,
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P_MII0_ETxEN,
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P_MII0_ERxD0,
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P_MII0_ERxD1,
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P_MII0_TxCLK,
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P_MII0_PHYINT,
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P_MII0_CRS,
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P_MII0_MDC,
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P_MII0_MDIO,
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0
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};
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static struct bfin_phydev_platform_data bfin_phydev_data[] = {
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{
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#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M)
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.addr = 3,
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#else
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.addr = 1,
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#endif
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.irq = IRQ_MAC_PHYINT,
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},
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};
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static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
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.phydev_number = 1,
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.phydev_data = bfin_phydev_data,
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.phy_mode = PHY_INTERFACE_MODE_MII,
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.mac_peripherals = bfin_mac_peripherals,
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#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M)
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.phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */
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#endif
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.vlan1_mask = 1,
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.vlan2_mask = 2,
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};
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static struct platform_device bfin_mii_bus = {
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.name = "bfin_mii_bus",
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.dev = {
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.platform_data = &bfin_mii_bus_data,
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}
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};
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static struct platform_device bfin_mac_device = {
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.name = "bfin_mac",
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.dev = {
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.platform_data = &bfin_mii_bus,
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}
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};
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#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M)
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static struct dsa_chip_data ksz8893m_switch_chip_data = {
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.mii_bus = &bfin_mii_bus.dev,
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.port_names = {
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NULL,
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"eth%d",
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"eth%d",
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"cpu",
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},
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};
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static struct dsa_platform_data ksz8893m_switch_data = {
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.nr_chips = 1,
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.netdev = &bfin_mac_device.dev,
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.chip = &ksz8893m_switch_chip_data,
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};
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static struct platform_device ksz8893m_switch_device = {
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.name = "dsa",
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.id = 0,
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.num_resources = 0,
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.dev.platform_data = &ksz8893m_switch_data,
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};
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#endif
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#endif
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#if IS_ENABLED(CONFIG_MTD_M25P80)
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static struct mtd_partition bfin_spi_flash_partitions[] = {
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{
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.name = "bootloader(spi)",
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.size = 0x00040000,
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.offset = 0,
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.mask_flags = MTD_CAP_ROM
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}, {
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.name = "linux kernel(spi)",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_APPEND,
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}
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};
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static struct flash_platform_data bfin_spi_flash_data = {
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.name = "m25p80",
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.parts = bfin_spi_flash_partitions,
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.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
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.type = "m25p16",
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};
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/* SPI flash chip (m25p64) */
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static struct bfin5xx_spi_chip spi_flash_chip_info = {
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.enable_dma = 0, /* use dma transfer with this chip*/
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};
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#endif
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#if IS_ENABLED(CONFIG_MMC_SPI)
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static struct bfin5xx_spi_chip mmc_spi_chip_info = {
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.enable_dma = 0,
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};
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#endif
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#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
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static const struct ad7877_platform_data bfin_ad7877_ts_info = {
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.model = 7877,
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.vref_delay_usecs = 50, /* internal, no capacitor */
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.x_plate_ohms = 419,
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.y_plate_ohms = 486,
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.pressure_max = 1000,
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.pressure_min = 0,
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.stopacq_polarity = 1,
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.first_conversion_delay = 3,
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.acquisition_time = 1,
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.averaging = 1,
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.pen_down_acc_interval = 1,
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};
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#endif
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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#if IS_ENABLED(CONFIG_MTD_M25P80)
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{
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/* the modalias must be the same as spi device driver name */
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.modalias = "m25p80", /* Name of spi_driver for this device */
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.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0, /* Framework bus number */
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.chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
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.platform_data = &bfin_spi_flash_data,
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.controller_data = &spi_flash_chip_info,
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.mode = SPI_MODE_3,
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},
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#endif
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#if IS_ENABLED(CONFIG_BFIN_MAC)
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#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M)
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{
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.modalias = "ksz8893m",
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.max_speed_hz = 5000000,
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.bus_num = 0,
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.chip_select = 1,
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.platform_data = NULL,
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.mode = SPI_MODE_3,
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},
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#endif
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#endif
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#if IS_ENABLED(CONFIG_MMC_SPI)
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{
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.modalias = "mmc_spi",
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.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 5,
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.controller_data = &mmc_spi_chip_info,
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.mode = SPI_MODE_3,
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},
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#endif
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#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
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{
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.modalias = "ad7877",
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.platform_data = &bfin_ad7877_ts_info,
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.irq = IRQ_PF8,
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.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 2,
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},
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#endif
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#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
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&& defined(CONFIG_SND_SOC_WM8731_SPI)
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{
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.modalias = "wm8731",
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.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 5,
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.mode = SPI_MODE_0,
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},
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#endif
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#if IS_ENABLED(CONFIG_SPI_SPIDEV)
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{
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.modalias = "spidev",
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.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 1,
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},
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#endif
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#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
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{
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.modalias = "bfin-lq035q1-spi",
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.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 1,
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.mode = SPI_CPHA | SPI_CPOL,
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},
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#endif
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};
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/* SPI controller data */
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#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
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/* SPI (0) */
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static struct bfin5xx_spi_master bfin_spi0_info = {
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.num_chipselect = 6,
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.enable_dma = 1, /* master has the ability to do dma transfer */
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.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
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};
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static struct resource bfin_spi0_resource[] = {
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[0] = {
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.start = SPI0_REGBASE,
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.end = SPI0_REGBASE + 0xFF,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = CH_SPI0,
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.end = CH_SPI0,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = IRQ_SPI0,
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.end = IRQ_SPI0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device bfin_spi0_device = {
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.name = "bfin-spi",
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.id = 0, /* Bus number */
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.num_resources = ARRAY_SIZE(bfin_spi0_resource),
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.resource = bfin_spi0_resource,
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.dev = {
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.platform_data = &bfin_spi0_info, /* Passed to driver */
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},
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};
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/* SPI (1) */
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static struct bfin5xx_spi_master bfin_spi1_info = {
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.num_chipselect = 6,
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.enable_dma = 1, /* master has the ability to do dma transfer */
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.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
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};
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static struct resource bfin_spi1_resource[] = {
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[0] = {
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.start = SPI1_REGBASE,
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.end = SPI1_REGBASE + 0xFF,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = CH_SPI1,
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.end = CH_SPI1,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = IRQ_SPI1,
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.end = IRQ_SPI1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device bfin_spi1_device = {
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.name = "bfin-spi",
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.id = 1, /* Bus number */
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.num_resources = ARRAY_SIZE(bfin_spi1_resource),
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.resource = bfin_spi1_resource,
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.dev = {
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.platform_data = &bfin_spi1_info, /* Passed to driver */
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},
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};
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#endif /* spi master and devices */
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#if IS_ENABLED(CONFIG_SERIAL_BFIN)
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|
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||
|
|
static struct resource bfin_uart0_resources[] = {
|
||
|
|
{
|
||
|
|
.start = UART0_THR,
|
||
|
|
.end = UART0_GCTL+2,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = IRQ_UART0_TX,
|
||
|
|
.end = IRQ_UART0_TX,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = IRQ_UART0_RX,
|
||
|
|
.end = IRQ_UART0_RX,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = IRQ_UART0_ERROR,
|
||
|
|
.end = IRQ_UART0_ERROR,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = CH_UART0_TX,
|
||
|
|
.end = CH_UART0_TX,
|
||
|
|
.flags = IORESOURCE_DMA,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = CH_UART0_RX,
|
||
|
|
.end = CH_UART0_RX,
|
||
|
|
.flags = IORESOURCE_DMA,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static unsigned short bfin_uart0_peripherals[] = {
|
||
|
|
P_UART0_TX, P_UART0_RX, 0
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device bfin_uart0_device = {
|
||
|
|
.name = "bfin-uart",
|
||
|
|
.id = 0,
|
||
|
|
.num_resources = ARRAY_SIZE(bfin_uart0_resources),
|
||
|
|
.resource = bfin_uart0_resources,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
|
||
|
|
},
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||
|
|
static struct resource bfin_uart1_resources[] = {
|
||
|
|
{
|
||
|
|
.start = UART1_THR,
|
||
|
|
.end = UART1_GCTL+2,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = IRQ_UART1_TX,
|
||
|
|
.end = IRQ_UART1_TX,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = IRQ_UART1_RX,
|
||
|
|
.end = IRQ_UART1_RX,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = IRQ_UART1_ERROR,
|
||
|
|
.end = IRQ_UART1_ERROR,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = CH_UART1_TX,
|
||
|
|
.end = CH_UART1_TX,
|
||
|
|
.flags = IORESOURCE_DMA,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = CH_UART1_RX,
|
||
|
|
.end = CH_UART1_RX,
|
||
|
|
.flags = IORESOURCE_DMA,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static unsigned short bfin_uart1_peripherals[] = {
|
||
|
|
P_UART1_TX, P_UART1_RX, 0
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device bfin_uart1_device = {
|
||
|
|
.name = "bfin-uart",
|
||
|
|
.id = 1,
|
||
|
|
.num_resources = ARRAY_SIZE(bfin_uart1_resources),
|
||
|
|
.resource = bfin_uart1_resources,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
|
||
|
|
},
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_BFIN_SIR)
|
||
|
|
#ifdef CONFIG_BFIN_SIR0
|
||
|
|
static struct resource bfin_sir0_resources[] = {
|
||
|
|
{
|
||
|
|
.start = 0xFFC00400,
|
||
|
|
.end = 0xFFC004FF,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = IRQ_UART0_RX,
|
||
|
|
.end = IRQ_UART0_RX+1,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = CH_UART0_RX,
|
||
|
|
.end = CH_UART0_RX+1,
|
||
|
|
.flags = IORESOURCE_DMA,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device bfin_sir0_device = {
|
||
|
|
.name = "bfin_sir",
|
||
|
|
.id = 0,
|
||
|
|
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
|
||
|
|
.resource = bfin_sir0_resources,
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_BFIN_SIR1
|
||
|
|
static struct resource bfin_sir1_resources[] = {
|
||
|
|
{
|
||
|
|
.start = 0xFFC02000,
|
||
|
|
.end = 0xFFC020FF,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = IRQ_UART1_RX,
|
||
|
|
.end = IRQ_UART1_RX+1,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = CH_UART1_RX,
|
||
|
|
.end = CH_UART1_RX+1,
|
||
|
|
.flags = IORESOURCE_DMA,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device bfin_sir1_device = {
|
||
|
|
.name = "bfin_sir",
|
||
|
|
.id = 1,
|
||
|
|
.num_resources = ARRAY_SIZE(bfin_sir1_resources),
|
||
|
|
.resource = bfin_sir1_resources,
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
|
||
|
|
static struct platform_device bfin_i2s = {
|
||
|
|
.name = "bfin-i2s",
|
||
|
|
.id = CONFIG_SND_BF5XX_SPORT_NUM,
|
||
|
|
/* TODO: add platform data here */
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
|
||
|
|
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
|
||
|
|
|
||
|
|
static struct resource bfin_twi0_resource[] = {
|
||
|
|
[0] = {
|
||
|
|
.start = TWI0_REGBASE,
|
||
|
|
.end = TWI0_REGBASE,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
[1] = {
|
||
|
|
.start = IRQ_TWI,
|
||
|
|
.end = IRQ_TWI,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device i2c_bfin_twi_device = {
|
||
|
|
.name = "i2c-bfin-twi",
|
||
|
|
.id = 0,
|
||
|
|
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
|
||
|
|
.resource = bfin_twi0_resource,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &bfin_twi0_pins,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
|
||
|
|
#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
|
||
|
|
{
|
||
|
|
I2C_BOARD_INFO("pcf8574_lcd", 0x22),
|
||
|
|
},
|
||
|
|
#endif
|
||
|
|
#if IS_ENABLED(CONFIG_INPUT_PCF8574)
|
||
|
|
{
|
||
|
|
I2C_BOARD_INFO("pcf8574_keypad", 0x27),
|
||
|
|
.irq = IRQ_PF8,
|
||
|
|
},
|
||
|
|
#endif
|
||
|
|
#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
|
||
|
|
{
|
||
|
|
I2C_BOARD_INFO("ssm2602", 0x1b),
|
||
|
|
},
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
|
||
|
|
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
||
|
|
static struct resource bfin_sport0_uart_resources[] = {
|
||
|
|
{
|
||
|
|
.start = SPORT0_TCR1,
|
||
|
|
.end = SPORT0_MRCS3+4,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = IRQ_SPORT0_RX,
|
||
|
|
.end = IRQ_SPORT0_RX+1,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = IRQ_SPORT0_ERROR,
|
||
|
|
.end = IRQ_SPORT0_ERROR,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static unsigned short bfin_sport0_peripherals[] = {
|
||
|
|
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
|
||
|
|
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device bfin_sport0_uart_device = {
|
||
|
|
.name = "bfin-sport-uart",
|
||
|
|
.id = 0,
|
||
|
|
.num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
|
||
|
|
.resource = bfin_sport0_uart_resources,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
|
||
|
|
},
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
||
|
|
static struct resource bfin_sport1_uart_resources[] = {
|
||
|
|
{
|
||
|
|
.start = SPORT1_TCR1,
|
||
|
|
.end = SPORT1_MRCS3+4,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = IRQ_SPORT1_RX,
|
||
|
|
.end = IRQ_SPORT1_RX+1,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = IRQ_SPORT1_ERROR,
|
||
|
|
.end = IRQ_SPORT1_ERROR,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static unsigned short bfin_sport1_peripherals[] = {
|
||
|
|
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
|
||
|
|
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device bfin_sport1_uart_device = {
|
||
|
|
.name = "bfin-sport-uart",
|
||
|
|
.id = 1,
|
||
|
|
.num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
|
||
|
|
.resource = bfin_sport1_uart_resources,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &bfin_sport1_peripherals, /* Passed to driver */
|
||
|
|
},
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
|
||
|
|
#include <linux/input.h>
|
||
|
|
#include <linux/gpio_keys.h>
|
||
|
|
|
||
|
|
static struct gpio_keys_button bfin_gpio_keys_table[] = {
|
||
|
|
{BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
|
||
|
|
{BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct gpio_keys_platform_data bfin_gpio_keys_data = {
|
||
|
|
.buttons = bfin_gpio_keys_table,
|
||
|
|
.nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device bfin_device_gpiokeys = {
|
||
|
|
.name = "gpio-keys",
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &bfin_gpio_keys_data,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_SDH_BFIN)
|
||
|
|
|
||
|
|
static struct bfin_sd_host bfin_sdh_data = {
|
||
|
|
.dma_chan = CH_RSI,
|
||
|
|
.irq_int0 = IRQ_RSI_INT0,
|
||
|
|
.pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device bf51x_sdh_device = {
|
||
|
|
.name = "bfin-sdh",
|
||
|
|
.id = 0,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &bfin_sdh_data,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static const unsigned int cclk_vlev_datasheet[] =
|
||
|
|
{
|
||
|
|
VRPAIR(VLEV_100, 400000000),
|
||
|
|
VRPAIR(VLEV_105, 426000000),
|
||
|
|
VRPAIR(VLEV_110, 500000000),
|
||
|
|
VRPAIR(VLEV_115, 533000000),
|
||
|
|
VRPAIR(VLEV_120, 600000000),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
|
||
|
|
.tuple_tab = cclk_vlev_datasheet,
|
||
|
|
.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
|
||
|
|
.vr_settling_time = 25 /* us */,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device bfin_dpmc = {
|
||
|
|
.name = "bfin dpmc",
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &bfin_dmpc_vreg_data,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device *stamp_devices[] __initdata = {
|
||
|
|
|
||
|
|
&bfin_dpmc,
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
|
||
|
|
&rtc_device,
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_BFIN_MAC)
|
||
|
|
&bfin_mii_bus,
|
||
|
|
&bfin_mac_device,
|
||
|
|
#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M)
|
||
|
|
&ksz8893m_switch_device,
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
|
||
|
|
&bfin_spi0_device,
|
||
|
|
&bfin_spi1_device,
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_SERIAL_BFIN)
|
||
|
|
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||
|
|
&bfin_uart0_device,
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||
|
|
&bfin_uart1_device,
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_BFIN_SIR)
|
||
|
|
#ifdef CONFIG_BFIN_SIR0
|
||
|
|
&bfin_sir0_device,
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_BFIN_SIR1
|
||
|
|
&bfin_sir1_device,
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
|
||
|
|
&i2c_bfin_twi_device,
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
|
||
|
|
&bfin_i2s,
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
|
||
|
|
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
||
|
|
&bfin_sport0_uart_device,
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
||
|
|
&bfin_sport1_uart_device,
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
|
||
|
|
&bfin_device_gpiokeys,
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_SDH_BFIN)
|
||
|
|
&bf51x_sdh_device,
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
|
||
|
|
&ezbrd_flash_device,
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init ezbrd_init(void)
|
||
|
|
{
|
||
|
|
printk(KERN_INFO "%s(): registering device resources\n", __func__);
|
||
|
|
i2c_register_board_info(0, bfin_i2c_board_info,
|
||
|
|
ARRAY_SIZE(bfin_i2c_board_info));
|
||
|
|
platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
|
||
|
|
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
|
||
|
|
/* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
|
||
|
|
peripheral_request(P_AMS2, "ParaFlash");
|
||
|
|
#if !IS_ENABLED(CONFIG_SPI_BFIN5XX)
|
||
|
|
peripheral_request(P_AMS3, "ParaFlash");
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
arch_initcall(ezbrd_init);
|
||
|
|
|
||
|
|
static struct platform_device *ezbrd_early_devices[] __initdata = {
|
||
|
|
#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
|
||
|
|
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||
|
|
&bfin_uart0_device,
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||
|
|
&bfin_uart1_device,
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
|
||
|
|
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
||
|
|
&bfin_sport0_uart_device,
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
||
|
|
&bfin_sport1_uart_device,
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
void __init native_machine_early_platform_add_devices(void)
|
||
|
|
{
|
||
|
|
printk(KERN_INFO "register early platform devices\n");
|
||
|
|
early_platform_add_devices(ezbrd_early_devices,
|
||
|
|
ARRAY_SIZE(ezbrd_early_devices));
|
||
|
|
}
|
||
|
|
|
||
|
|
void native_machine_restart(char *cmd)
|
||
|
|
{
|
||
|
|
/* workaround reboot hang when booting from SPI */
|
||
|
|
if ((bfin_read_SYSCR() & 0x7) == 0x3)
|
||
|
|
bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
|
||
|
|
}
|
||
|
|
|
||
|
|
int bfin_get_ether_addr(char *addr)
|
||
|
|
{
|
||
|
|
/* the MAC is stored in OTP memory page 0xDF */
|
||
|
|
u32 ret;
|
||
|
|
u64 otp_mac;
|
||
|
|
u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
|
||
|
|
|
||
|
|
ret = otp_read(0xDF, 0x00, &otp_mac);
|
||
|
|
if (!(ret & 0x1)) {
|
||
|
|
char *otp_mac_p = (char *)&otp_mac;
|
||
|
|
for (ret = 0; ret < 6; ++ret)
|
||
|
|
addr[ret] = otp_mac_p[5 - ret];
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(bfin_get_ether_addr);
|