86 lines
1.9 KiB
C
86 lines
1.9 KiB
C
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/*
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* Blackfin cache control code (simpler control-style functions)
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*
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* Copyright 2004-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <asm/blackfin.h>
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#include <asm/cplbinit.h>
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/* Invalidate the Entire Data cache by
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* clearing DMC[1:0] bits
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*/
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void blackfin_invalidate_entire_dcache(void)
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{
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u32 dmem = bfin_read_DMEM_CONTROL();
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bfin_write_DMEM_CONTROL(dmem & ~0xc);
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SSYNC();
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bfin_write_DMEM_CONTROL(dmem);
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SSYNC();
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}
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/* Invalidate the Entire Instruction cache by
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* clearing IMC bit
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*/
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void blackfin_invalidate_entire_icache(void)
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{
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u32 imem = bfin_read_IMEM_CONTROL();
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bfin_write_IMEM_CONTROL(imem & ~0x4);
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SSYNC();
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bfin_write_IMEM_CONTROL(imem);
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SSYNC();
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}
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#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
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static void
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bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
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unsigned long cplb_data, unsigned long mem_control,
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unsigned long mem_mask)
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{
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int i;
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#ifdef CONFIG_L1_PARITY_CHECK
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u32 ctrl;
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if (cplb_addr == DCPLB_ADDR0) {
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ctrl = bfin_read32(mem_control) | (1 << RDCHK);
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CSYNC();
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bfin_write32(mem_control, ctrl);
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SSYNC();
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}
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#endif
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for (i = 0; i < MAX_CPLBS; i++) {
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bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
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bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);
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}
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_enable_cplb(mem_control, mem_mask);
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}
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#ifdef CONFIG_BFIN_ICACHE
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void bfin_icache_init(struct cplb_entry *icplb_tbl)
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{
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bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
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(IMC | ENICPLB));
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}
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#endif
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#ifdef CONFIG_BFIN_DCACHE
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void bfin_dcache_init(struct cplb_entry *dcplb_tbl)
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{
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/*
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* Anomaly notes:
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* 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
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* register, so that the port preferences for DAG0 and DAG1 are set
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* to port B
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*/
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bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,
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(DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));
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}
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#endif
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#endif
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