122 lines
3.2 KiB
C
122 lines
3.2 KiB
C
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/*
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* arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory
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*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/linkage.h>
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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#include <asm/clocks.h>
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#include <asm/mem_init.h>
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#include <asm/dpmc.h>
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#ifdef CONFIG_BF60x
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#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
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#define CGU_DIV_VAL \
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((CONFIG_CCLK_DIV << CSEL_OFFSET) | \
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(CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \
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(CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \
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(CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \
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(CONFIG_DCLK_DIV << DSEL_OFFSET))
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#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
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#if ((CONFIG_BFIN_DCLK != 125) && \
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(CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \
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(CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \
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(CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
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#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
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#endif
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#else
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#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
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#define PLL_CTL_VAL \
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(((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
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(PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
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#endif
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__attribute__((l1_text))
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static void do_sync(void)
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{
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__builtin_bfin_ssync();
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}
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__attribute__((l1_text))
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void init_clocks(void)
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{
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/* Kill any active DMAs as they may trigger external memory accesses
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* in the middle of reprogramming things, and that'll screw us up.
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* For example, any automatic DMAs left by U-Boot for splash screens.
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*/
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#ifdef CONFIG_BF60x
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init_cgu(CGU_DIV_VAL, CGU_CTL_VAL);
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init_dmc(CONFIG_BFIN_DCLK);
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#else
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size_t i;
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for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
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struct dma_register *dma = dma_io_base_addr[i];
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dma->cfg = 0;
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}
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do_sync();
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#ifdef SIC_IWR0
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bfin_write_SIC_IWR0(IWR_ENABLE(0));
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# ifdef SIC_IWR1
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/* BF52x system reset does not properly reset SIC_IWR1 which
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* will screw up the bootrom as it relies on MDMA0/1 waking it
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* up from IDLE instructions. See this report for more info:
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* http://blackfin.uclinux.org/gf/tracker/4323
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*/
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if (ANOMALY_05000435)
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bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
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else
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bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
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# endif
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# ifdef SIC_IWR2
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bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
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# endif
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#else
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bfin_write_SIC_IWR(IWR_ENABLE(0));
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#endif
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do_sync();
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#ifdef EBIU_SDGCTL
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bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
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do_sync();
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#endif
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#ifdef CLKBUFOE
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bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
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do_sync();
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__asm__ __volatile__("IDLE;");
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#endif
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bfin_write_PLL_LOCKCNT(0x300);
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do_sync();
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/* We always write PLL_CTL thus avoiding Anomaly 05000242 */
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bfin_write16(PLL_CTL, PLL_CTL_VAL);
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__asm__ __volatile__("IDLE;");
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bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
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#ifdef EBIU_SDGCTL
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bfin_write_EBIU_SDRRC(mem_SDRRC);
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bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL);
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#else
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bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
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do_sync();
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bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
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bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
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bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
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bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
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#ifdef CONFIG_MEM_EBIU_DDRQUE
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bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
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#endif
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#endif
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#endif
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do_sync();
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bfin_read16(0);
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}
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