308 lines
8.0 KiB
C
308 lines
8.0 KiB
C
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/*
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* Copyright (C) NEC Electronics Corporation 2004-2006
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*
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* This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
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*
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* Copyright 2001 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/delay.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/bootinfo.h>
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#include <asm/emma/emma2rh.h>
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static void emma2rh_irq_enable(struct irq_data *d)
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{
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unsigned int irq = d->irq - EMMA2RH_IRQ_BASE;
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u32 reg_value, reg_bitmask, reg_index;
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reg_index = EMMA2RH_BHIF_INT_EN_0 +
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(EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
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reg_value = emma2rh_in32(reg_index);
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reg_bitmask = 0x1 << (irq % 32);
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emma2rh_out32(reg_index, reg_value | reg_bitmask);
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}
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static void emma2rh_irq_disable(struct irq_data *d)
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{
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unsigned int irq = d->irq - EMMA2RH_IRQ_BASE;
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u32 reg_value, reg_bitmask, reg_index;
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reg_index = EMMA2RH_BHIF_INT_EN_0 +
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(EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
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reg_value = emma2rh_in32(reg_index);
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reg_bitmask = 0x1 << (irq % 32);
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emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
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}
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struct irq_chip emma2rh_irq_controller = {
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.name = "emma2rh_irq",
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.irq_mask = emma2rh_irq_disable,
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.irq_unmask = emma2rh_irq_enable,
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};
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void emma2rh_irq_init(void)
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{
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u32 i;
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for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
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irq_set_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
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&emma2rh_irq_controller,
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handle_level_irq, "level");
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}
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static void emma2rh_sw_irq_enable(struct irq_data *d)
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{
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unsigned int irq = d->irq - EMMA2RH_SW_IRQ_BASE;
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u32 reg;
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reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
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reg |= 1 << irq;
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emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
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}
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static void emma2rh_sw_irq_disable(struct irq_data *d)
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{
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unsigned int irq = d->irq - EMMA2RH_SW_IRQ_BASE;
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u32 reg;
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reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
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reg &= ~(1 << irq);
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emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
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}
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struct irq_chip emma2rh_sw_irq_controller = {
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.name = "emma2rh_sw_irq",
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.irq_mask = emma2rh_sw_irq_disable,
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.irq_unmask = emma2rh_sw_irq_enable,
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};
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void emma2rh_sw_irq_init(void)
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{
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u32 i;
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for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
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irq_set_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
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&emma2rh_sw_irq_controller,
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handle_level_irq, "level");
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}
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static void emma2rh_gpio_irq_enable(struct irq_data *d)
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{
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unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE;
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u32 reg;
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reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
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reg |= 1 << irq;
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emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
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}
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static void emma2rh_gpio_irq_disable(struct irq_data *d)
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{
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unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE;
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u32 reg;
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reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
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reg &= ~(1 << irq);
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emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
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}
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static void emma2rh_gpio_irq_ack(struct irq_data *d)
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{
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unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE;
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emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
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}
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static void emma2rh_gpio_irq_mask_ack(struct irq_data *d)
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{
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unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE;
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u32 reg;
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emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
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reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
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reg &= ~(1 << irq);
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emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
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}
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struct irq_chip emma2rh_gpio_irq_controller = {
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.name = "emma2rh_gpio_irq",
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.irq_ack = emma2rh_gpio_irq_ack,
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.irq_mask = emma2rh_gpio_irq_disable,
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.irq_mask_ack = emma2rh_gpio_irq_mask_ack,
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.irq_unmask = emma2rh_gpio_irq_enable,
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};
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void emma2rh_gpio_irq_init(void)
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{
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u32 i;
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for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
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irq_set_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
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&emma2rh_gpio_irq_controller,
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handle_edge_irq, "edge");
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}
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static struct irqaction irq_cascade = {
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.handler = no_action,
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.flags = IRQF_NO_THREAD,
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.name = "cascade",
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.dev_id = NULL,
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.next = NULL,
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};
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/*
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* the first level int-handler will jump here if it is a emma2rh irq
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*/
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void emma2rh_irq_dispatch(void)
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{
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u32 intStatus;
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u32 bitmask;
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u32 i;
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intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) &
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emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
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#ifdef EMMA2RH_SW_CASCADE
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if (intStatus & (1UL << EMMA2RH_SW_CASCADE)) {
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u32 swIntStatus;
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swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
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& emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
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for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
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if (swIntStatus & bitmask) {
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do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
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return;
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}
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}
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}
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/* Skip S/W interrupt */
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intStatus &= ~(1UL << EMMA2RH_SW_CASCADE);
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#endif
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for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
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if (intStatus & bitmask) {
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do_IRQ(EMMA2RH_IRQ_BASE + i);
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return;
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}
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}
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intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) &
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emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
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#ifdef EMMA2RH_GPIO_CASCADE
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if (intStatus & (1UL << (EMMA2RH_GPIO_CASCADE % 32))) {
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u32 gpioIntStatus;
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gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
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& emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
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for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
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if (gpioIntStatus & bitmask) {
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do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
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return;
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}
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}
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}
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/* Skip GPIO interrupt */
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intStatus &= ~(1UL << (EMMA2RH_GPIO_CASCADE % 32));
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#endif
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for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
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if (intStatus & bitmask) {
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do_IRQ(EMMA2RH_IRQ_BASE + i);
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return;
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}
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}
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intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) &
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emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
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for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
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if (intStatus & bitmask) {
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do_IRQ(EMMA2RH_IRQ_BASE + i);
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return;
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}
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}
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}
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void __init arch_init_irq(void)
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{
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u32 reg;
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/* by default, interrupts are disabled. */
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emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
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emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
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emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
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emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
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emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
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emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
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emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
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clear_c0_status(0xff00);
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set_c0_status(0x0400);
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#define GPIO_PCI (0xf<<15)
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/* setup GPIO interrupt for PCI interface */
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/* direction input */
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reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
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emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
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/* disable interrupt */
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reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
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emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
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/* level triggerd */
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reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
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emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
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reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
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emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
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/* interrupt clear */
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emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
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/* init all controllers */
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emma2rh_irq_init();
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emma2rh_sw_irq_init();
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emma2rh_gpio_irq_init();
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mips_cpu_irq_init();
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/* setup cascade interrupts */
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setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
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setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
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setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP7)
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do_IRQ(MIPS_CPU_IRQ_BASE + 7);
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else if (pending & STATUSF_IP2)
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emma2rh_irq_dispatch();
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else if (pending & STATUSF_IP1)
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do_IRQ(MIPS_CPU_IRQ_BASE + 1);
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else if (pending & STATUSF_IP0)
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do_IRQ(MIPS_CPU_IRQ_BASE + 0);
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else
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spurious_interrupt();
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}
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