69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
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* Carsten Langgaard <carstenl@mips.com>
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* Steven J. Hill <sjhill@mips.com>
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*/
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#ifndef _MIPS_MALTAINT_H
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#define _MIPS_MALTAINT_H
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#include <linux/irqchip/mips-gic.h>
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/*
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* Interrupts 0..15 are used for Malta ISA compatible interrupts
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*/
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#define MALTA_INT_BASE 0
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/* CPU interrupt offsets */
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#define MIPSCPU_INT_SW0 0
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#define MIPSCPU_INT_SW1 1
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#define MIPSCPU_INT_MB0 2
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#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
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#define MIPSCPU_INT_GIC MIPSCPU_INT_MB0 /* GIC chained interrupt */
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#define MIPSCPU_INT_MB1 3
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#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
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#define MIPSCPU_INT_MB2 4
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#define MIPSCPU_INT_MB3 5
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#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
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#define MIPSCPU_INT_MB4 6
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#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4
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/*
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* Interrupts 96..127 are used for Soc-it Classic interrupts
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*/
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#define MSC01C_INT_BASE 96
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/* SOC-it Classic interrupt offsets */
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#define MSC01C_INT_TMR 0
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#define MSC01C_INT_PCI 1
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/*
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* Interrupts 96..127 are used for Soc-it EIC interrupts
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*/
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#define MSC01E_INT_BASE 96
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/* SOC-it EIC interrupt offsets */
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#define MSC01E_INT_SW0 1
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#define MSC01E_INT_SW1 2
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#define MSC01E_INT_MB0 3
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#define MSC01E_INT_I8259A MSC01E_INT_MB0
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#define MSC01E_INT_MB1 4
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#define MSC01E_INT_SMI MSC01E_INT_MB1
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#define MSC01E_INT_MB2 5
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#define MSC01E_INT_MB3 6
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#define MSC01E_INT_COREHI MSC01E_INT_MB3
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#define MSC01E_INT_MB4 7
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#define MSC01E_INT_CORELO MSC01E_INT_MB4
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#define MSC01E_INT_TMR 8
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#define MSC01E_INT_PCI 9
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#define MSC01E_INT_PERFCTR 10
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#define MSC01E_INT_CPUCTR 11
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/* GIC external interrupts */
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#define GIC_INT_I8259A GIC_SHARED_TO_HWIRQ(3)
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#endif /* !(_MIPS_MALTAINT_H) */
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