213 lines
6.0 KiB
C
213 lines
6.0 KiB
C
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/kernel.h>
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#include <linux/threads.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/string.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/mips-extns.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
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{
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uint32_t coremask, value;
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int count, resetreg;
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coremask = (1 << core);
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/* Enable CPU clock in case of 8xx/3xx */
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if (!cpu_is_xlpii()) {
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value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
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value &= ~coremask;
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nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
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}
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/* On 9XX, mark coherent first */
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if (cpu_is_xlp9xx()) {
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value = nlm_read_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE);
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value &= ~coremask;
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nlm_write_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE, value);
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}
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/* Remove CPU Reset */
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resetreg = cpu_is_xlp9xx() ? SYS_9XX_CPU_RESET : SYS_CPU_RESET;
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value = nlm_read_sys_reg(sysbase, resetreg);
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value &= ~coremask;
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nlm_write_sys_reg(sysbase, resetreg, value);
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/* We are done on 9XX */
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if (cpu_is_xlp9xx())
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return 1;
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/* Poll for CPU to mark itself coherent on other type of XLP */
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count = 100000;
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do {
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value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
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} while ((value & coremask) != 0 && --count > 0);
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return count != 0;
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}
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static int wait_for_cpus(int cpu, int bootcpu)
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{
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volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
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int i, count, notready;
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count = 0x800000;
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do {
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notready = nlm_threads_per_core;
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for (i = 0; i < nlm_threads_per_core; i++)
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if (cpu_ready[cpu + i] || (cpu + i) == bootcpu)
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--notready;
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} while (notready != 0 && --count > 0);
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return count != 0;
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}
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static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
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{
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struct nlm_soc_info *nodep;
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uint64_t syspcibase, fusebase;
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uint32_t syscoremask, mask, fusemask;
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int core, n, cpu, ncores;
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for (n = 0; n < NLM_NR_NODES; n++) {
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if (n != 0) {
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/* check if node exists and is online */
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if (cpu_is_xlp9xx()) {
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int b = xlp9xx_get_socbus(n);
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pr_info("Node %d SoC PCI bus %d.\n", n, b);
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if (b == 0)
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break;
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} else {
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syspcibase = nlm_get_sys_pcibase(n);
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if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
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break;
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}
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nlm_node_init(n);
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}
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/* read cores in reset from SYS */
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nodep = nlm_get_node(n);
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if (cpu_is_xlp9xx()) {
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fusebase = nlm_get_fuse_regbase(n);
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fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6);
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switch (read_c0_prid() & PRID_IMP_MASK) {
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case PRID_IMP_NETLOGIC_XLP5XX:
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mask = 0xff;
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break;
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case PRID_IMP_NETLOGIC_XLP9XX:
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default:
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mask = 0xfffff;
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break;
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}
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} else {
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fusemask = nlm_read_sys_reg(nodep->sysbase,
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SYS_EFUSE_DEVICE_CFG_STATUS0);
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switch (read_c0_prid() & PRID_IMP_MASK) {
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case PRID_IMP_NETLOGIC_XLP3XX:
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mask = 0xf;
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break;
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case PRID_IMP_NETLOGIC_XLP2XX:
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mask = 0x3;
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break;
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case PRID_IMP_NETLOGIC_XLP8XX:
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default:
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mask = 0xff;
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break;
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}
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}
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/*
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* Fused out cores are set in the fusemask, and the remaining
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* cores are renumbered to range 0 .. nactive-1
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*/
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syscoremask = (1 << hweight32(~fusemask & mask)) - 1;
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pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask);
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ncores = nlm_cores_per_node();
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for (core = 0; core < ncores; core++) {
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/* we will be on node 0 core 0 */
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if (n == 0 && core == 0)
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continue;
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/* see if the core exists */
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if ((syscoremask & (1 << core)) == 0)
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continue;
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/* see if at least the first hw thread is enabled */
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cpu = (n * ncores + core) * NLM_THREADS_PER_CORE;
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if (!cpumask_test_cpu(cpu, wakeup_mask))
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continue;
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/* wake up the core */
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if (!xlp_wakeup_core(nodep->sysbase, n, core))
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continue;
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/* core is up */
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nodep->coremask |= 1u << core;
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/* spin until the hw threads sets their ready */
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if (!wait_for_cpus(cpu, 0))
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pr_err("Node %d : timeout core %d\n", n, core);
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}
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}
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}
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void xlp_wakeup_secondary_cpus()
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{
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/*
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* In case of u-boot, the secondaries are in reset
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* first wakeup core 0 threads
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*/
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xlp_boot_core0_siblings();
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if (!wait_for_cpus(0, 0))
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pr_err("Node 0 : timeout core 0\n");
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/* now get other cores out of reset */
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xlp_enable_secondary_cores(&nlm_cpumask);
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}
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