333 lines
9.1 KiB
C
333 lines
9.1 KiB
C
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/*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/msi.h>
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#include <linux/mm.h>
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#include <linux/irq.h>
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#include <linux/irqdesc.h>
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#include <linux/console.h>
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#include <asm/io.h>
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#include <asm/netlogic/interrupt.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/mips-extns.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#include <asm/netlogic/xlp-hal/pcibus.h>
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#include <asm/netlogic/xlp-hal/bridge.h>
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static void *pci_config_base;
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#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
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/* PCI ops */
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static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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u32 data;
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u32 *cfgaddr;
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where &= ~3;
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if (cpu_is_xlp9xx()) {
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/* be very careful on SoC buses */
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if (bus->number == 0) {
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/* Scan only existing nodes - uboot bug? */
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if (PCI_SLOT(devfn) != 0 ||
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!nlm_node_present(PCI_FUNC(devfn)))
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return 0xffffffff;
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} else if (bus->parent->number == 0) { /* SoC bus */
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if (PCI_SLOT(devfn) == 0) /* b.0.0 hangs */
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return 0xffffffff;
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if (devfn == 44) /* b.5.4 hangs */
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return 0xffffffff;
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}
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} else if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) {
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return 0xffffffff;
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}
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cfgaddr = (u32 *)(pci_config_base +
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pci_cfg_addr(bus->number, devfn, where));
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data = *cfgaddr;
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return data;
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}
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static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
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int where, u32 data)
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{
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u32 *cfgaddr;
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cfgaddr = (u32 *)(pci_config_base +
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pci_cfg_addr(bus->number, devfn, where & ~3));
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*cfgaddr = data;
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}
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static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u32 data;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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data = pci_cfg_read_32bit(bus, devfn, where);
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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data = pci_cfg_read_32bit(bus, devfn, where);
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else
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data = val;
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pci_cfg_write_32bit(bus, devfn, where, data);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops nlm_pci_ops = {
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.read = nlm_pcibios_read,
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.write = nlm_pcibios_write
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};
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static struct resource nlm_pci_mem_resource = {
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.name = "XLP PCI MEM",
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.start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
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.end = 0xdfffffffUL,
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.flags = IORESOURCE_MEM,
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};
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static struct resource nlm_pci_io_resource = {
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.name = "XLP IO MEM",
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.start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
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.end = 0x17ffffffUL,
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.flags = IORESOURCE_IO,
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};
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struct pci_controller nlm_pci_controller = {
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.index = 0,
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.pci_ops = &nlm_pci_ops,
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.mem_resource = &nlm_pci_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_resource = &nlm_pci_io_resource,
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.io_offset = 0x00000000UL,
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};
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struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
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{
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struct pci_bus *bus, *p;
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bus = dev->bus;
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if (cpu_is_xlp9xx()) {
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/* find bus with grand parent number == 0 */
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for (p = bus->parent; p && p->parent && p->parent->number != 0;
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p = p->parent)
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bus = p;
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return (p && p->parent) ? bus->self : NULL;
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} else {
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/* Find the bridge on bus 0 */
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for (p = bus->parent; p && p->number != 0; p = p->parent)
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bus = p;
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return p ? bus->self : NULL;
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}
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}
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int xlp_socdev_to_node(const struct pci_dev *lnkdev)
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{
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if (cpu_is_xlp9xx())
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return PCI_FUNC(lnkdev->bus->self->devfn);
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else
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return PCI_SLOT(lnkdev->devfn) / 8;
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct pci_dev *lnkdev;
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int lnkfunc, node;
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/*
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* For XLP PCIe, there is an IRQ per Link, find out which
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* link the device is on to assign interrupts
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*/
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lnkdev = xlp_get_pcie_link(dev);
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if (lnkdev == NULL)
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return 0;
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lnkfunc = PCI_FUNC(lnkdev->devfn);
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node = xlp_socdev_to_node(lnkdev);
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return nlm_irq_to_xirq(node, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc));
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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/*
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* If big-endian, enable hardware byteswap on the PCIe bridges.
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* This will make both the SoC and PCIe devices behave consistently with
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* readl/writel.
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*/
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#ifdef __BIG_ENDIAN
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static void xlp_config_pci_bswap(int node, int link)
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{
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uint64_t nbubase, lnkbase;
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u32 reg;
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nbubase = nlm_get_bridge_regbase(node);
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lnkbase = nlm_get_pcie_base(node, link);
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/*
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* Enable byte swap in hardware. Program each link's PCIe SWAP regions
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* from the link's address ranges.
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*/
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if (cpu_is_xlp9xx()) {
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reg = nlm_read_bridge_reg(nbubase,
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BRIDGE_9XX_PCIEMEM_BASE0 + link);
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nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_MEM_BASE, reg);
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reg = nlm_read_bridge_reg(nbubase,
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BRIDGE_9XX_PCIEMEM_LIMIT0 + link);
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nlm_write_pci_reg(lnkbase,
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PCIE_9XX_BYTE_SWAP_MEM_LIM, reg | 0xfff);
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reg = nlm_read_bridge_reg(nbubase,
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BRIDGE_9XX_PCIEIO_BASE0 + link);
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nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_IO_BASE, reg);
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reg = nlm_read_bridge_reg(nbubase,
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BRIDGE_9XX_PCIEIO_LIMIT0 + link);
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nlm_write_pci_reg(lnkbase,
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PCIE_9XX_BYTE_SWAP_IO_LIM, reg | 0xfff);
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} else {
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reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
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nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);
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reg = nlm_read_bridge_reg(nbubase,
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BRIDGE_PCIEMEM_LIMIT0 + link);
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nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff);
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reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
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nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);
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reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
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nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
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}
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}
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#else
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/* Swap configuration not needed in little-endian mode */
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static inline void xlp_config_pci_bswap(int node, int link) {}
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#endif /* __BIG_ENDIAN */
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static int __init pcibios_init(void)
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{
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uint64_t pciebase;
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int link, n;
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u32 reg;
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/* Firmware assigns PCI resources */
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pci_set_flags(PCI_PROBE_ONLY);
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pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
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/* Extend IO port for memory mapped io */
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ioport_resource.start = 0;
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ioport_resource.end = ~0;
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for (n = 0; n < NLM_NR_NODES; n++) {
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if (!nlm_node_present(n))
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continue;
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for (link = 0; link < PCIE_NLINKS; link++) {
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pciebase = nlm_get_pcie_base(n, link);
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if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
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continue;
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xlp_config_pci_bswap(n, link);
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xlp_init_node_msi_irqs(n, link);
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/* put in intpin and irq - u-boot does not */
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reg = nlm_read_pci_reg(pciebase, 0xf);
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reg &= ~0x1ffu;
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reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link);
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nlm_write_pci_reg(pciebase, 0xf, reg);
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pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
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}
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}
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set_io_port_base(CKSEG1);
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nlm_pci_controller.io_map_base = CKSEG1;
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register_pci_controller(&nlm_pci_controller);
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pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
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&nlm_pci_mem_resource);
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return 0;
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}
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arch_initcall(pcibios_init);
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