116 lines
3.8 KiB
C
116 lines
3.8 KiB
C
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_CACHEFLUSH_H
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#define _ASM_POWERPC_CACHEFLUSH_H
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#ifdef __KERNEL__
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#include <linux/mm.h>
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#include <asm/cputable.h>
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#include <asm/cpu_has_feature.h>
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/*
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* No cache flushing is required when address mappings are changed,
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* because the caches on PowerPCs are physically addressed.
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*/
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_icache_page(vma, page) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *page);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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extern void flush_icache_range(unsigned long, unsigned long);
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extern void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr,
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int len);
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extern void __flush_dcache_icache(void *page_va);
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extern void flush_dcache_icache_page(struct page *page);
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#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
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extern void __flush_dcache_icache_phys(unsigned long physaddr);
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#else
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static inline void __flush_dcache_icache_phys(unsigned long physaddr)
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{
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BUG();
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}
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#endif
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#ifdef CONFIG_PPC32
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/*
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* Write any modified data cache blocks out to memory and invalidate them.
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* Does not invalidate the corresponding instruction cache blocks.
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*/
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static inline void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
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unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
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unsigned long i;
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for (i = 0; i < size >> L1_CACHE_SHIFT; i++, addr += L1_CACHE_BYTES)
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dcbf(addr);
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mb(); /* sync */
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}
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/*
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* Write any modified data cache blocks out to memory.
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* Does not invalidate the corresponding cache lines (especially for
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* any corresponding instruction cache).
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*/
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static inline void clean_dcache_range(unsigned long start, unsigned long stop)
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{
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void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
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unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
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unsigned long i;
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for (i = 0; i < size >> L1_CACHE_SHIFT; i++, addr += L1_CACHE_BYTES)
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dcbst(addr);
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mb(); /* sync */
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}
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/*
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* Like above, but invalidate the D-cache. This is used by the 8xx
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* to invalidate the cache so the PPC core doesn't get stale data
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* from the CPM (no cache snooping here :-).
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*/
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static inline void invalidate_dcache_range(unsigned long start,
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unsigned long stop)
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{
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void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
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unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
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unsigned long i;
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for (i = 0; i < size >> L1_CACHE_SHIFT; i++, addr += L1_CACHE_BYTES)
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dcbi(addr);
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mb(); /* sync */
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}
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#endif /* CONFIG_PPC32 */
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#ifdef CONFIG_PPC64
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extern void flush_dcache_range(unsigned long start, unsigned long stop);
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extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
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extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
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#endif
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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flush_icache_user_range(vma, page, vaddr, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_CACHEFLUSH_H */
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