160 lines
6.1 KiB
C
160 lines
6.1 KiB
C
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/*
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* Performance event support - PowerPC classic/server specific definitions.
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*
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* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <asm/hw_irq.h>
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#include <linux/device.h>
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#include <uapi/asm/perf_event.h>
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/* Update perf_event_print_debug() if this changes */
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#define MAX_HWEVENTS 8
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#define MAX_EVENT_ALTERNATIVES 8
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#define MAX_LIMITED_HWCOUNTERS 2
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struct perf_event;
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/*
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* This struct provides the constants and functions needed to
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* describe the PMU on a particular POWER-family CPU.
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*/
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struct power_pmu {
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const char *name;
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int n_counter;
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int max_alternatives;
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unsigned long add_fields;
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unsigned long test_adder;
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int (*compute_mmcr)(u64 events[], int n_ev,
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unsigned int hwc[], unsigned long mmcr[],
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struct perf_event *pevents[]);
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int (*get_constraint)(u64 event_id, unsigned long *mskp,
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unsigned long *valp);
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int (*get_alternatives)(u64 event_id, unsigned int flags,
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u64 alt[]);
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u64 (*bhrb_filter_map)(u64 branch_sample_type);
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void (*config_bhrb)(u64 pmu_bhrb_filter);
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void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
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int (*limited_pmc_event)(u64 event_id);
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u32 flags;
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const struct attribute_group **attr_groups;
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int n_generic;
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int *generic_events;
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int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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/* BHRB entries in the PMU */
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int bhrb_nr;
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};
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/*
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* Values for power_pmu.flags
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*/
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#define PPMU_LIMITED_PMC5_6 0x00000001 /* PMC5/6 have limited function */
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#define PPMU_ALT_SIPR 0x00000002 /* uses alternate posn for SIPR/HV */
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#define PPMU_NO_SIPR 0x00000004 /* no SIPR/HV in MMCRA at all */
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#define PPMU_NO_CONT_SAMPLING 0x00000008 /* no continuous sampling */
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#define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */
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#define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */
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#define PPMU_HAS_SIER 0x00000040 /* Has SIER */
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#define PPMU_ARCH_207S 0x00000080 /* PMC is architecture v2.07S */
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/*
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* Values for flags to get_alternatives()
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*/
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#define PPMU_LIMITED_PMC_OK 1 /* can put this on a limited PMC */
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#define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */
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#define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */
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extern int register_power_pmu(struct power_pmu *);
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struct pt_regs;
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extern unsigned long perf_misc_flags(struct pt_regs *regs);
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extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
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extern unsigned long int read_bhrb(int n);
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/*
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* Only override the default definitions in include/linux/perf_event.h
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* if we have hardware PMU support.
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*/
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#ifdef CONFIG_PPC_PERF_CTRS
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#define perf_misc_flags(regs) perf_misc_flags(regs)
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#endif
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/*
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* The power_pmu.get_constraint function returns a 32/64-bit value and
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* a 32/64-bit mask that express the constraints between this event_id and
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* other events.
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*
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* The value and mask are divided up into (non-overlapping) bitfields
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* of three different types:
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*
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* Select field: this expresses the constraint that some set of bits
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* in MMCR* needs to be set to a specific value for this event_id. For a
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* select field, the mask contains 1s in every bit of the field, and
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* the value contains a unique value for each possible setting of the
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* MMCR* bits. The constraint checking code will ensure that two events
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* that set the same field in their masks have the same value in their
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* value dwords.
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*
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* Add field: this expresses the constraint that there can be at most
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* N events in a particular class. A field of k bits can be used for
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* N <= 2^(k-1) - 1. The mask has the most significant bit of the field
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* set (and the other bits 0), and the value has only the least significant
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* bit of the field set. In addition, the 'add_fields' and 'test_adder'
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* in the struct power_pmu for this processor come into play. The
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* add_fields value contains 1 in the LSB of the field, and the
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* test_adder contains 2^(k-1) - 1 - N in the field.
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*
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* NAND field: this expresses the constraint that you may not have events
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* in all of a set of classes. (For example, on PPC970, you can't select
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* events from the FPU, ISU and IDU simultaneously, although any two are
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* possible.) For N classes, the field is N+1 bits wide, and each class
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* is assigned one bit from the least-significant N bits. The mask has
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* only the most-significant bit set, and the value has only the bit
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* for the event_id's class set. The test_adder has the least significant
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* bit set in the field.
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*
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* If an event_id is not subject to the constraint expressed by a particular
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* field, then it will have 0 in both the mask and value for that field.
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*/
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extern ssize_t power_events_sysfs_show(struct device *dev,
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struct device_attribute *attr, char *page);
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/*
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* EVENT_VAR() is same as PMU_EVENT_VAR with a suffix.
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*
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* Having a suffix allows us to have aliases in sysfs - eg: the generic
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* event 'cpu-cycles' can have two entries in sysfs: 'cpu-cycles' and
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* 'PM_CYC' where the latter is the name by which the event is known in
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* POWER CPU specification.
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*
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* Similarly, some hardware and cache events use the same event code. Eg.
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* on POWER8, both "cache-references" and "L1-dcache-loads" events refer
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* to the same event, PM_LD_REF_L1. The suffix, allows us to have two
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* sysfs objects for the same event and thus two entries/aliases in sysfs.
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*/
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#define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix
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#define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr
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#define EVENT_ATTR(_name, _id, _suffix) \
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PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), _id, \
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power_events_sysfs_show)
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#define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g)
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#define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g)
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#define CACHE_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _c)
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#define CACHE_EVENT_PTR(_id) EVENT_PTR(_id, _c)
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#define POWER_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _p)
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#define POWER_EVENT_PTR(_id) EVENT_PTR(_id, _p)
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