90 lines
2.1 KiB
C
90 lines
2.1 KiB
C
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/*
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* Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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struct pt_regs;
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/*
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* We don't allow single-stepping an mtmsrd that would clear
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* MSR_RI, since that would make the exception unrecoverable.
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* Since we need to single-step to proceed from a breakpoint,
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* we don't allow putting a breakpoint on an mtmsrd instruction.
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* Similarly we don't allow breakpoints on rfid instructions.
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* These macros tell us if an instruction is a mtmsrd or rfid.
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* Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
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* and an mtmsrd (64-bit).
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*/
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#define IS_MTMSRD(instr) (((instr) & 0xfc0007be) == 0x7c000124)
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#define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024)
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#define IS_RFI(instr) (((instr) & 0xfc0007fe) == 0x4c000064)
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/* Emulate instructions that cause a transfer of control. */
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extern int emulate_step(struct pt_regs *regs, unsigned int instr);
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enum instruction_type {
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COMPUTE, /* arith/logical/CR op, etc. */
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LOAD,
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LOAD_MULTI,
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LOAD_FP,
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LOAD_VMX,
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LOAD_VSX,
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STORE,
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STORE_MULTI,
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STORE_FP,
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STORE_VMX,
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STORE_VSX,
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LARX,
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STCX,
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BRANCH,
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MFSPR,
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MTSPR,
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CACHEOP,
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BARRIER,
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SYSCALL,
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MFMSR,
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MTMSR,
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RFI,
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INTERRUPT,
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UNKNOWN
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};
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#define INSTR_TYPE_MASK 0x1f
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/* Load/store flags, ORed in with type */
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#define SIGNEXT 0x20
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#define UPDATE 0x40 /* matches bit in opcode 31 instructions */
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#define BYTEREV 0x80
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/* Cacheop values, ORed in with type */
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#define CACHEOP_MASK 0x700
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#define DCBST 0
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#define DCBF 0x100
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#define DCBTST 0x200
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#define DCBT 0x300
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#define ICBI 0x400
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/* Size field in type word */
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#define SIZE(n) ((n) << 8)
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#define GETSIZE(w) ((w) >> 8)
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#define MKOP(t, f, s) ((t) | (f) | SIZE(s))
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struct instruction_op {
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int type;
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int reg;
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unsigned long val;
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/* For LOAD/STORE/LARX/STCX */
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unsigned long ea;
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int update_reg;
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/* For MFSPR */
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int spr;
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};
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extern int analyse_instr(struct instruction_op *op, struct pt_regs *regs,
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unsigned int instr);
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