344 lines
8.7 KiB
C
344 lines
8.7 KiB
C
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/*
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*
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* Utility functions for the Freescale MPC52xx.
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*
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* Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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*/
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#undef DEBUG
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/of_platform.h>
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#include <linux/of_gpio.h>
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#include <linux/export.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/mpc52xx.h>
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/* MPC5200 device tree match tables */
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static const struct of_device_id mpc52xx_xlb_ids[] __initconst = {
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{ .compatible = "fsl,mpc5200-xlb", },
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{ .compatible = "mpc5200-xlb", },
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{}
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};
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static const struct of_device_id mpc52xx_bus_ids[] __initconst = {
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{ .compatible = "fsl,mpc5200-immr", },
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{ .compatible = "fsl,mpc5200b-immr", },
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{ .compatible = "simple-bus", },
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/* depreciated matches; shouldn't be used in new device trees */
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{ .compatible = "fsl,lpb", },
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{ .type = "builtin", .compatible = "mpc5200", }, /* efika */
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{ .type = "soc", .compatible = "mpc5200", }, /* lite5200 */
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{}
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};
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/*
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* This variable is mapped in mpc52xx_map_wdt() and used in mpc52xx_restart().
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* Permanent mapping is required because mpc52xx_restart() can be called
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* from interrupt context while node mapping (which calls ioremap())
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* cannot be used at such point.
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*/
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static DEFINE_SPINLOCK(mpc52xx_lock);
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static struct mpc52xx_gpt __iomem *mpc52xx_wdt;
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static struct mpc52xx_cdm __iomem *mpc52xx_cdm;
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/*
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* Configure the XLB arbiter settings to match what Linux expects.
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*/
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void __init
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mpc5200_setup_xlb_arbiter(void)
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{
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struct device_node *np;
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struct mpc52xx_xlb __iomem *xlb;
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np = of_find_matching_node(NULL, mpc52xx_xlb_ids);
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xlb = of_iomap(np, 0);
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of_node_put(np);
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if (!xlb) {
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printk(KERN_ERR __FILE__ ": "
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"Error mapping XLB in mpc52xx_setup_cpu(). "
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"Expect some abnormal behavior\n");
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return;
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}
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/* Configure the XLB Arbiter priorities */
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out_be32(&xlb->master_pri_enable, 0xff);
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out_be32(&xlb->master_priority, 0x11111111);
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/*
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* Disable XLB pipelining
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* (cfr errate 292. We could do this only just before ATA PIO
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* transaction and re-enable it afterwards ...)
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* Not needed on MPC5200B.
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*/
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if ((mfspr(SPRN_SVR) & MPC5200_SVR_MASK) == MPC5200_SVR)
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out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS);
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iounmap(xlb);
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}
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/*
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* This variable is mapped in mpc52xx_map_common_devices and
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* used in mpc5200_psc_ac97_gpio_reset().
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*/
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static DEFINE_SPINLOCK(gpio_lock);
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struct mpc52xx_gpio __iomem *simple_gpio;
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struct mpc52xx_gpio_wkup __iomem *wkup_gpio;
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/**
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* mpc52xx_declare_of_platform_devices: register internal devices and children
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* of the localplus bus to the of_platform
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* bus.
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*/
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void __init mpc52xx_declare_of_platform_devices(void)
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{
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/* Find all the 'platform' devices and register them. */
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if (of_platform_populate(NULL, mpc52xx_bus_ids, NULL, NULL))
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pr_err(__FILE__ ": Error while populating devices from DT\n");
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}
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/*
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* match tables used by mpc52xx_map_common_devices()
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*/
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static const struct of_device_id mpc52xx_gpt_ids[] __initconst = {
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{ .compatible = "fsl,mpc5200-gpt", },
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{ .compatible = "mpc5200-gpt", }, /* old */
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{}
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};
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static const struct of_device_id mpc52xx_cdm_ids[] __initconst = {
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{ .compatible = "fsl,mpc5200-cdm", },
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{ .compatible = "mpc5200-cdm", }, /* old */
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{}
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};
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static const struct of_device_id mpc52xx_gpio_simple[] __initconst = {
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{ .compatible = "fsl,mpc5200-gpio", },
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{}
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};
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static const struct of_device_id mpc52xx_gpio_wkup[] __initconst = {
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{ .compatible = "fsl,mpc5200-gpio-wkup", },
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{}
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};
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/**
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* mpc52xx_map_common_devices: iomap devices required by common code
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*/
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void __init
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mpc52xx_map_common_devices(void)
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{
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struct device_node *np;
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/* mpc52xx_wdt is mapped here and used in mpc52xx_restart,
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* possibly from a interrupt context. wdt is only implement
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* on a gpt0, so check has-wdt property before mapping.
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*/
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for_each_matching_node(np, mpc52xx_gpt_ids) {
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if (of_get_property(np, "fsl,has-wdt", NULL) ||
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of_get_property(np, "has-wdt", NULL)) {
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mpc52xx_wdt = of_iomap(np, 0);
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of_node_put(np);
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break;
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}
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}
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/* Clock Distribution Module, used by PSC clock setting function */
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np = of_find_matching_node(NULL, mpc52xx_cdm_ids);
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mpc52xx_cdm = of_iomap(np, 0);
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of_node_put(np);
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/* simple_gpio registers */
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np = of_find_matching_node(NULL, mpc52xx_gpio_simple);
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simple_gpio = of_iomap(np, 0);
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of_node_put(np);
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/* wkup_gpio registers */
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np = of_find_matching_node(NULL, mpc52xx_gpio_wkup);
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wkup_gpio = of_iomap(np, 0);
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of_node_put(np);
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}
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/**
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* mpc52xx_set_psc_clkdiv: Set clock divider in the CDM for PSC ports
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*
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* @psc_id: id of psc port; must be 1,2,3 or 6
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* @clkdiv: clock divider value to put into CDM PSC register.
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*/
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int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
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{
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unsigned long flags;
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u16 __iomem *reg;
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u32 val;
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u32 mask;
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u32 mclken_div;
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if (!mpc52xx_cdm)
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return -ENODEV;
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mclken_div = 0x8000 | (clkdiv & 0x1FF);
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switch (psc_id) {
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case 1: reg = &mpc52xx_cdm->mclken_div_psc1; mask = 0x20; break;
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case 2: reg = &mpc52xx_cdm->mclken_div_psc2; mask = 0x40; break;
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case 3: reg = &mpc52xx_cdm->mclken_div_psc3; mask = 0x80; break;
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case 6: reg = &mpc52xx_cdm->mclken_div_psc6; mask = 0x10; break;
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default:
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return -ENODEV;
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}
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/* Set the rate and enable the clock */
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spin_lock_irqsave(&mpc52xx_lock, flags);
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out_be16(reg, mclken_div);
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val = in_be32(&mpc52xx_cdm->clk_enables);
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out_be32(&mpc52xx_cdm->clk_enables, val | mask);
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spin_unlock_irqrestore(&mpc52xx_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(mpc52xx_set_psc_clkdiv);
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/**
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* mpc52xx_get_xtal_freq - Get SYS_XTAL_IN frequency for a device
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*
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* @node: device node
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*
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* Returns the frequency of the external oscillator clock connected
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* to the SYS_XTAL_IN pin, or 0 if it cannot be determined.
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*/
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unsigned int mpc52xx_get_xtal_freq(struct device_node *node)
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{
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u32 val;
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unsigned int freq;
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if (!mpc52xx_cdm)
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return 0;
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freq = mpc5xxx_get_bus_frequency(node);
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if (!freq)
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return 0;
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if (in_8(&mpc52xx_cdm->ipb_clk_sel) & 0x1)
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freq *= 2;
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val = in_be32(&mpc52xx_cdm->rstcfg);
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if (val & (1 << 5))
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freq *= 8;
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else
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freq *= 4;
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if (val & (1 << 6))
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freq /= 12;
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else
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freq /= 16;
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return freq;
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}
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EXPORT_SYMBOL(mpc52xx_get_xtal_freq);
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/**
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* mpc52xx_restart: ppc_md->restart hook for mpc5200 using the watchdog timer
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*/
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void __noreturn mpc52xx_restart(char *cmd)
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{
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local_irq_disable();
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/* Turn on the watchdog and wait for it to expire.
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* It effectively does a reset. */
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if (mpc52xx_wdt) {
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out_be32(&mpc52xx_wdt->mode, 0x00000000);
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out_be32(&mpc52xx_wdt->count, 0x000000ff);
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out_be32(&mpc52xx_wdt->mode, 0x00009004);
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} else
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printk(KERN_ERR __FILE__ ": "
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"mpc52xx_restart: Can't access wdt. "
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"Restart impossible, system halted.\n");
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while (1);
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}
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#define PSC1_RESET 0x1
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#define PSC1_SYNC 0x4
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#define PSC1_SDATA_OUT 0x1
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#define PSC2_RESET 0x2
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#define PSC2_SYNC (0x4<<4)
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#define PSC2_SDATA_OUT (0x1<<4)
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#define MPC52xx_GPIO_PSC1_MASK 0x7
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#define MPC52xx_GPIO_PSC2_MASK (0x7<<4)
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/**
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* mpc5200_psc_ac97_gpio_reset: Use gpio pins to reset the ac97 bus
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*
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* @psc: psc number to reset (only psc 1 and 2 support ac97)
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*/
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int mpc5200_psc_ac97_gpio_reset(int psc_number)
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{
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unsigned long flags;
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u32 gpio;
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u32 mux;
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int out;
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int reset;
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int sync;
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if ((!simple_gpio) || (!wkup_gpio))
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return -ENODEV;
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switch (psc_number) {
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case 0:
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reset = PSC1_RESET; /* AC97_1_RES */
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sync = PSC1_SYNC; /* AC97_1_SYNC */
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out = PSC1_SDATA_OUT; /* AC97_1_SDATA_OUT */
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gpio = MPC52xx_GPIO_PSC1_MASK;
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break;
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case 1:
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reset = PSC2_RESET; /* AC97_2_RES */
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sync = PSC2_SYNC; /* AC97_2_SYNC */
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out = PSC2_SDATA_OUT; /* AC97_2_SDATA_OUT */
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gpio = MPC52xx_GPIO_PSC2_MASK;
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break;
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default:
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pr_err(__FILE__ ": Unable to determine PSC, no ac97 "
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"cold-reset will be performed\n");
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return -ENODEV;
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}
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spin_lock_irqsave(&gpio_lock, flags);
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/* Reconfiure pin-muxing to gpio */
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mux = in_be32(&simple_gpio->port_config);
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out_be32(&simple_gpio->port_config, mux & (~gpio));
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/* enable gpio pins for output */
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setbits8(&wkup_gpio->wkup_gpioe, reset);
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setbits32(&simple_gpio->simple_gpioe, sync | out);
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setbits8(&wkup_gpio->wkup_ddr, reset);
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setbits32(&simple_gpio->simple_ddr, sync | out);
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/* Assert cold reset */
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clrbits32(&simple_gpio->simple_dvo, sync | out);
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clrbits8(&wkup_gpio->wkup_dvo, reset);
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/* wait for 1 us */
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udelay(1);
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/* Deassert reset */
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setbits8(&wkup_gpio->wkup_dvo, reset);
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/* wait at least 200ns */
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/* 7 ~= (200ns * timebase) / ns2sec */
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__delay(7);
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/* Restore pin-muxing */
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out_be32(&simple_gpio->port_config, mux);
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spin_unlock_irqrestore(&gpio_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(mpc5200_psc_ac97_gpio_reset);
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