362 lines
8.5 KiB
C
362 lines
8.5 KiB
C
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/*
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* This file implements the DMA operations for NVLink devices. The NPU
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* devices all point to the same iommu table as the parent PCI device.
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*
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* Copyright Alistair Popple, IBM Corporation 2015.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General Public
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* License as published by the Free Software Foundation.
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*/
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#include <linux/export.h>
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#include <linux/pci.h>
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#include <linux/memblock.h>
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#include <linux/iommu.h>
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#include <asm/iommu.h>
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#include <asm/pnv-pci.h>
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#include <asm/msi_bitmap.h>
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#include <asm/opal.h>
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#include "powernv.h"
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#include "pci.h"
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/*
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* Other types of TCE cache invalidation are not functional in the
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* hardware.
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*/
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static struct pci_dev *get_pci_dev(struct device_node *dn)
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{
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return PCI_DN(dn)->pcidev;
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}
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/* Given a NPU device get the associated PCI device. */
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struct pci_dev *pnv_pci_get_gpu_dev(struct pci_dev *npdev)
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{
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struct device_node *dn;
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struct pci_dev *gpdev;
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/* Get assoicated PCI device */
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dn = of_parse_phandle(npdev->dev.of_node, "ibm,gpu", 0);
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if (!dn)
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return NULL;
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gpdev = get_pci_dev(dn);
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of_node_put(dn);
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return gpdev;
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}
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EXPORT_SYMBOL(pnv_pci_get_gpu_dev);
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/* Given the real PCI device get a linked NPU device. */
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struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index)
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{
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struct device_node *dn;
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struct pci_dev *npdev;
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/* Get assoicated PCI device */
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dn = of_parse_phandle(gpdev->dev.of_node, "ibm,npu", index);
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if (!dn)
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return NULL;
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npdev = get_pci_dev(dn);
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of_node_put(dn);
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return npdev;
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}
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EXPORT_SYMBOL(pnv_pci_get_npu_dev);
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#define NPU_DMA_OP_UNSUPPORTED() \
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dev_err_once(dev, "%s operation unsupported for NVLink devices\n", \
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__func__)
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static void *dma_npu_alloc(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag,
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unsigned long attrs)
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{
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NPU_DMA_OP_UNSUPPORTED();
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return NULL;
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}
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static void dma_npu_free(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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unsigned long attrs)
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{
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NPU_DMA_OP_UNSUPPORTED();
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}
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static dma_addr_t dma_npu_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction,
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unsigned long attrs)
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{
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NPU_DMA_OP_UNSUPPORTED();
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return 0;
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}
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static int dma_npu_map_sg(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction,
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unsigned long attrs)
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{
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NPU_DMA_OP_UNSUPPORTED();
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return 0;
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}
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static int dma_npu_dma_supported(struct device *dev, u64 mask)
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{
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NPU_DMA_OP_UNSUPPORTED();
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return 0;
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}
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static u64 dma_npu_get_required_mask(struct device *dev)
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{
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NPU_DMA_OP_UNSUPPORTED();
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return 0;
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}
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static struct dma_map_ops dma_npu_ops = {
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.map_page = dma_npu_map_page,
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.map_sg = dma_npu_map_sg,
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.alloc = dma_npu_alloc,
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.free = dma_npu_free,
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.dma_supported = dma_npu_dma_supported,
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.get_required_mask = dma_npu_get_required_mask,
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};
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/*
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* Returns the PE assoicated with the PCI device of the given
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* NPU. Returns the linked pci device if pci_dev != NULL.
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*/
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static struct pnv_ioda_pe *get_gpu_pci_dev_and_pe(struct pnv_ioda_pe *npe,
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struct pci_dev **gpdev)
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{
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struct pnv_phb *phb;
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struct pci_controller *hose;
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struct pci_dev *pdev;
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struct pnv_ioda_pe *pe;
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struct pci_dn *pdn;
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pdev = pnv_pci_get_gpu_dev(npe->pdev);
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if (!pdev)
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return NULL;
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pdn = pci_get_pdn(pdev);
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if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
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return NULL;
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hose = pci_bus_to_host(pdev->bus);
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phb = hose->private_data;
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pe = &phb->ioda.pe_array[pdn->pe_number];
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if (gpdev)
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*gpdev = pdev;
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return pe;
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}
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long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
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struct iommu_table *tbl)
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{
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struct pnv_phb *phb = npe->phb;
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int64_t rc;
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const unsigned long size = tbl->it_indirect_levels ?
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tbl->it_level_size : tbl->it_size;
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const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
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const __u64 win_size = tbl->it_size << tbl->it_page_shift;
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pe_info(npe, "Setting up window %llx..%llx pg=%lx\n",
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start_addr, start_addr + win_size - 1,
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IOMMU_PAGE_SIZE(tbl));
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rc = opal_pci_map_pe_dma_window(phb->opal_id,
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npe->pe_number,
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npe->pe_number,
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tbl->it_indirect_levels + 1,
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__pa(tbl->it_base),
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size << 3,
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IOMMU_PAGE_SIZE(tbl));
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if (rc) {
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pe_err(npe, "Failed to configure TCE table, err %lld\n", rc);
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return rc;
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}
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pnv_pci_phb3_tce_invalidate_entire(phb, false);
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/* Add the table to the list so its TCE cache will get invalidated */
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pnv_pci_link_table_and_group(phb->hose->node, num,
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tbl, &npe->table_group);
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return 0;
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}
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long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num)
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{
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struct pnv_phb *phb = npe->phb;
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int64_t rc;
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pe_info(npe, "Removing DMA window\n");
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rc = opal_pci_map_pe_dma_window(phb->opal_id, npe->pe_number,
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npe->pe_number,
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0/* levels */, 0/* table address */,
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0/* table size */, 0/* page size */);
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if (rc) {
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pe_err(npe, "Unmapping failed, ret = %lld\n", rc);
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return rc;
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}
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pnv_pci_phb3_tce_invalidate_entire(phb, false);
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pnv_pci_unlink_table_and_group(npe->table_group.tables[num],
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&npe->table_group);
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return 0;
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}
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/*
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* Enables 32 bit DMA on NPU.
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*/
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static void pnv_npu_dma_set_32(struct pnv_ioda_pe *npe)
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{
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struct pci_dev *gpdev;
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struct pnv_ioda_pe *gpe;
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int64_t rc;
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/*
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* Find the assoicated PCI devices and get the dma window
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* information from there.
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*/
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if (!npe->pdev || !(npe->flags & PNV_IODA_PE_DEV))
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return;
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gpe = get_gpu_pci_dev_and_pe(npe, &gpdev);
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if (!gpe)
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return;
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rc = pnv_npu_set_window(npe, 0, gpe->table_group.tables[0]);
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/*
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* We don't initialise npu_pe->tce32_table as we always use
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* dma_npu_ops which are nops.
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*/
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set_dma_ops(&npe->pdev->dev, &dma_npu_ops);
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}
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/*
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* Enables bypass mode on the NPU. The NPU only supports one
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* window per link, so bypass needs to be explicitly enabled or
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* disabled. Unlike for a PHB3 bypass and non-bypass modes can't be
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* active at the same time.
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*/
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static int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe)
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{
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struct pnv_phb *phb = npe->phb;
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int64_t rc = 0;
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phys_addr_t top = memblock_end_of_DRAM();
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if (phb->type != PNV_PHB_NPU || !npe->pdev)
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return -EINVAL;
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rc = pnv_npu_unset_window(npe, 0);
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if (rc != OPAL_SUCCESS)
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return rc;
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/* Enable the bypass window */
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top = roundup_pow_of_two(top);
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dev_info(&npe->pdev->dev, "Enabling bypass for PE %d\n",
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npe->pe_number);
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rc = opal_pci_map_pe_dma_window_real(phb->opal_id,
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npe->pe_number, npe->pe_number,
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0 /* bypass base */, top);
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if (rc == OPAL_SUCCESS)
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pnv_pci_phb3_tce_invalidate_entire(phb, false);
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return rc;
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}
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void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass)
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{
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int i;
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struct pnv_phb *phb;
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struct pci_dn *pdn;
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struct pnv_ioda_pe *npe;
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struct pci_dev *npdev;
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for (i = 0; ; ++i) {
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npdev = pnv_pci_get_npu_dev(gpdev, i);
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if (!npdev)
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break;
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pdn = pci_get_pdn(npdev);
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if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
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return;
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phb = pci_bus_to_host(npdev->bus)->private_data;
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/* We only do bypass if it's enabled on the linked device */
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npe = &phb->ioda.pe_array[pdn->pe_number];
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if (bypass) {
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dev_info(&npdev->dev,
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"Using 64-bit DMA iommu bypass\n");
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pnv_npu_dma_set_bypass(npe);
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} else {
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dev_info(&npdev->dev, "Using 32-bit DMA via iommu\n");
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pnv_npu_dma_set_32(npe);
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}
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}
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}
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/* Switch ownership from platform code to external user (e.g. VFIO) */
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void pnv_npu_take_ownership(struct pnv_ioda_pe *npe)
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{
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struct pnv_phb *phb = npe->phb;
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int64_t rc;
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/*
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* Note: NPU has just a single TVE in the hardware which means that
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* while used by the kernel, it can have either 32bit window or
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* DMA bypass but never both. So we deconfigure 32bit window only
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* if it was enabled at the moment of ownership change.
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*/
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if (npe->table_group.tables[0]) {
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pnv_npu_unset_window(npe, 0);
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return;
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}
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/* Disable bypass */
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rc = opal_pci_map_pe_dma_window_real(phb->opal_id,
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npe->pe_number, npe->pe_number,
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0 /* bypass base */, 0);
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if (rc) {
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pe_err(npe, "Failed to disable bypass, err %lld\n", rc);
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return;
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}
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pnv_pci_phb3_tce_invalidate_entire(npe->phb, false);
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}
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struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
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{
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struct pnv_phb *phb = npe->phb;
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struct pci_bus *pbus = phb->hose->bus;
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struct pci_dev *npdev, *gpdev = NULL, *gptmp;
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struct pnv_ioda_pe *gpe = get_gpu_pci_dev_and_pe(npe, &gpdev);
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if (!gpe || !gpdev)
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return NULL;
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list_for_each_entry(npdev, &pbus->devices, bus_list) {
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gptmp = pnv_pci_get_gpu_dev(npdev);
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if (gptmp != gpdev)
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continue;
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pe_info(gpe, "Attached NPU %s\n", dev_name(&npdev->dev));
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iommu_group_add_device(gpe->table_group.group, &npdev->dev);
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}
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return gpe;
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}
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