179 lines
6.0 KiB
C
179 lines
6.0 KiB
C
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/*
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* pgtsrmmu.h: SRMMU page table defines and code.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _SPARC_PGTSRMMU_H
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#define _SPARC_PGTSRMMU_H
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#include <asm/page.h>
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#ifdef __ASSEMBLY__
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#include <asm/thread_info.h> /* TI_UWINMASK for WINDOW_FLUSH */
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#endif
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/* Number of contexts is implementation-dependent; 64k is the most we support */
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#define SRMMU_MAX_CONTEXTS 65536
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/* PMD_SHIFT determines the size of the area a second-level page table entry can map */
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#define SRMMU_REAL_PMD_SHIFT 18
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#define SRMMU_REAL_PMD_SIZE (1UL << SRMMU_REAL_PMD_SHIFT)
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#define SRMMU_REAL_PMD_MASK (~(SRMMU_REAL_PMD_SIZE-1))
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#define SRMMU_REAL_PMD_ALIGN(__addr) (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define SRMMU_PGDIR_SHIFT 24
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#define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT)
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#define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1))
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#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
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#define SRMMU_REAL_PTRS_PER_PTE 64
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#define SRMMU_REAL_PTRS_PER_PMD 64
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#define SRMMU_PTRS_PER_PGD 256
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#define SRMMU_REAL_PTE_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PTE*4)
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#define SRMMU_PMD_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PMD*4)
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#define SRMMU_PGD_TABLE_SIZE (SRMMU_PTRS_PER_PGD*4)
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/*
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* To support pagetables in highmem, Linux introduces APIs which
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* return struct page* and generally manipulate page tables when
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* they are not mapped into kernel space. Our hardware page tables
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* are smaller than pages. We lump hardware tabes into big, page sized
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* software tables.
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*
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* PMD_SHIFT determines the size of the area a second-level page table entry
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* can map, and our pmd_t is 16 times larger than normal. The values which
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* were once defined here are now generic for 4c and srmmu, so they're
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* found in pgtable.h.
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*/
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#define SRMMU_PTRS_PER_PMD 4
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/* Definition of the values in the ET field of PTD's and PTE's */
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#define SRMMU_ET_MASK 0x3
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#define SRMMU_ET_INVALID 0x0
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#define SRMMU_ET_PTD 0x1
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#define SRMMU_ET_PTE 0x2
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#define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
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/* Physical page extraction from PTP's and PTE's. */
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#define SRMMU_CTX_PMASK 0xfffffff0
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#define SRMMU_PTD_PMASK 0xfffffff0
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#define SRMMU_PTE_PMASK 0xffffff00
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/* The pte non-page bits. Some notes:
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* 1) cache, dirty, valid, and ref are frobbable
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* for both supervisor and user pages.
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* 2) exec and write will only give the desired effect
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* on user pages
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* 3) use priv and priv_readonly for changing the
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* characteristics of supervisor ptes
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*/
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#define SRMMU_CACHE 0x80
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#define SRMMU_DIRTY 0x40
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#define SRMMU_REF 0x20
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#define SRMMU_NOREAD 0x10
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#define SRMMU_EXEC 0x08
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#define SRMMU_WRITE 0x04
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#define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */
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#define SRMMU_PRIV 0x1c
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#define SRMMU_PRIV_RDONLY 0x18
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#define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
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/* SRMMU swap entry encoding
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*
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* We use 5 bits for the type and 19 for the offset. This gives us
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* 32 swapfiles of 4GB each. Encoding looks like:
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*
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* oooooooooooooooooootttttRRRRRRRR
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* fedcba9876543210fedcba9876543210
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*
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* The bottom 7 bits are reserved for protection and status bits, especially
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* PRESENT.
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*/
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#define SRMMU_SWP_TYPE_MASK 0x1f
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#define SRMMU_SWP_TYPE_SHIFT 7
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#define SRMMU_SWP_OFF_MASK 0xfffff
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#define SRMMU_SWP_OFF_SHIFT (SRMMU_SWP_TYPE_SHIFT + 5)
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/* Some day I will implement true fine grained access bits for
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* user pages because the SRMMU gives us the capabilities to
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* enforce all the protection levels that vma's can have.
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* XXX But for now...
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*/
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#define SRMMU_PAGE_NONE __pgprot(SRMMU_CACHE | \
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SRMMU_PRIV | SRMMU_REF)
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#define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \
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SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
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#define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
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SRMMU_EXEC | SRMMU_REF)
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#define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
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SRMMU_EXEC | SRMMU_REF)
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#define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
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SRMMU_DIRTY | SRMMU_REF)
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/* SRMMU Register addresses in ASI 0x4. These are valid for all
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* current SRMMU implementations that exist.
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*/
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#define SRMMU_CTRL_REG 0x00000000
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#define SRMMU_CTXTBL_PTR 0x00000100
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#define SRMMU_CTX_REG 0x00000200
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#define SRMMU_FAULT_STATUS 0x00000300
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#define SRMMU_FAULT_ADDR 0x00000400
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#define WINDOW_FLUSH(tmp1, tmp2) \
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mov 0, tmp1; \
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98: ld [%g6 + TI_UWINMASK], tmp2; \
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orcc %g0, tmp2, %g0; \
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add tmp1, 1, tmp1; \
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bne 98b; \
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save %sp, -64, %sp; \
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99: subcc tmp1, 1, tmp1; \
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bne 99b; \
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restore %g0, %g0, %g0;
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#ifndef __ASSEMBLY__
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extern unsigned long last_valid_pfn;
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/* This makes sense. Honest it does - Anton */
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/* XXX Yes but it's ugly as sin. FIXME. -KMW */
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extern void *srmmu_nocache_pool;
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#define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
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#define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
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#define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
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/* Accessing the MMU control register. */
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unsigned int srmmu_get_mmureg(void);
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void srmmu_set_mmureg(unsigned long regval);
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void srmmu_set_ctable_ptr(unsigned long paddr);
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void srmmu_set_context(int context);
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int srmmu_get_context(void);
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unsigned int srmmu_get_fstatus(void);
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unsigned int srmmu_get_faddr(void);
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/* This is guaranteed on all SRMMU's. */
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static inline void srmmu_flush_whole_tlb(void)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
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"r" (0x400), /* Flush entire TLB!! */
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"i" (ASI_M_FLUSH_PROBE) : "memory");
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}
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static inline int
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srmmu_get_pte (unsigned long addr)
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{
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register unsigned long entry;
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__asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
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"=r" (entry):
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"r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
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return entry;
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}
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#endif /* !(__ASSEMBLY__) */
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#endif /* !(_SPARC_PGTSRMMU_H) */
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