132 lines
4.6 KiB
C
132 lines
4.6 KiB
C
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/*
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* winmacro.h: Window loading-unloading macros.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _SPARC_WINMACRO_H
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#define _SPARC_WINMACRO_H
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#include <asm/ptrace.h>
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/* Store the register window onto the 8-byte aligned area starting
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* at %reg. It might be %sp, it might not, we don't care.
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*/
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#define STORE_WINDOW(reg) \
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std %l0, [%reg + RW_L0]; \
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std %l2, [%reg + RW_L2]; \
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std %l4, [%reg + RW_L4]; \
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std %l6, [%reg + RW_L6]; \
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std %i0, [%reg + RW_I0]; \
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std %i2, [%reg + RW_I2]; \
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std %i4, [%reg + RW_I4]; \
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std %i6, [%reg + RW_I6];
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/* Load a register window from the area beginning at %reg. */
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#define LOAD_WINDOW(reg) \
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ldd [%reg + RW_L0], %l0; \
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ldd [%reg + RW_L2], %l2; \
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ldd [%reg + RW_L4], %l4; \
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ldd [%reg + RW_L6], %l6; \
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ldd [%reg + RW_I0], %i0; \
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ldd [%reg + RW_I2], %i2; \
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ldd [%reg + RW_I4], %i4; \
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ldd [%reg + RW_I6], %i6;
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/* Loading and storing struct pt_reg trap frames. */
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#define LOAD_PT_INS(base_reg) \
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ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
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ldd [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \
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ldd [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \
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ldd [%base_reg + STACKFRAME_SZ + PT_I6], %i6;
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#define LOAD_PT_GLOBALS(base_reg) \
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ld [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \
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ldd [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \
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ldd [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
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ldd [%base_reg + STACKFRAME_SZ + PT_G6], %g6;
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#define LOAD_PT_YREG(base_reg, scratch) \
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ld [%base_reg + STACKFRAME_SZ + PT_Y], %scratch; \
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wr %scratch, 0x0, %y;
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#define LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
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ld [%base_reg + STACKFRAME_SZ + PT_PSR], %pt_psr; \
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ld [%base_reg + STACKFRAME_SZ + PT_PC], %pt_pc; \
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ld [%base_reg + STACKFRAME_SZ + PT_NPC], %pt_npc;
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#define LOAD_PT_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \
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LOAD_PT_YREG(base_reg, scratch) \
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LOAD_PT_INS(base_reg) \
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LOAD_PT_GLOBALS(base_reg) \
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LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc)
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#define STORE_PT_INS(base_reg) \
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std %i0, [%base_reg + STACKFRAME_SZ + PT_I0]; \
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std %i2, [%base_reg + STACKFRAME_SZ + PT_I2]; \
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std %i4, [%base_reg + STACKFRAME_SZ + PT_I4]; \
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std %i6, [%base_reg + STACKFRAME_SZ + PT_I6];
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#define STORE_PT_GLOBALS(base_reg) \
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st %g1, [%base_reg + STACKFRAME_SZ + PT_G1]; \
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std %g2, [%base_reg + STACKFRAME_SZ + PT_G2]; \
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std %g4, [%base_reg + STACKFRAME_SZ + PT_G4]; \
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std %g6, [%base_reg + STACKFRAME_SZ + PT_G6];
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#define STORE_PT_YREG(base_reg, scratch) \
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rd %y, %scratch; \
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st %scratch, [%base_reg + STACKFRAME_SZ + PT_Y];
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#define STORE_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
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st %pt_psr, [%base_reg + STACKFRAME_SZ + PT_PSR]; \
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st %pt_pc, [%base_reg + STACKFRAME_SZ + PT_PC]; \
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st %pt_npc, [%base_reg + STACKFRAME_SZ + PT_NPC];
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#define STORE_PT_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \
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STORE_PT_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \
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STORE_PT_GLOBALS(base_reg) \
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STORE_PT_YREG(base_reg, g_scratch) \
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STORE_PT_INS(base_reg)
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#define SAVE_BOLIXED_USER_STACK(cur_reg, scratch) \
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ld [%cur_reg + TI_W_SAVED], %scratch; \
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sll %scratch, 2, %scratch; \
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add %scratch, %cur_reg, %scratch; \
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st %sp, [%scratch + TI_RWIN_SPTRS]; \
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sub %scratch, %cur_reg, %scratch; \
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sll %scratch, 4, %scratch; \
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add %scratch, %cur_reg, %scratch; \
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STORE_WINDOW(scratch + TI_REG_WINDOW); \
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sub %scratch, %cur_reg, %scratch; \
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srl %scratch, 6, %scratch; \
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add %scratch, 1, %scratch; \
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st %scratch, [%cur_reg + TI_W_SAVED];
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#ifdef CONFIG_SMP
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#define LOAD_CURRENT(dest_reg, idreg) \
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661: rd %tbr, %idreg; \
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srl %idreg, 10, %idreg; \
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and %idreg, 0xc, %idreg; \
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.section .cpuid_patch, "ax"; \
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/* Instruction location. */ \
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.word 661b; \
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/* SUN4D implementation. */ \
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lda [%g0] ASI_M_VIKING_TMP1, %idreg; \
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sll %idreg, 2, %idreg; \
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nop; \
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/* LEON implementation. */ \
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rd %asr17, %idreg; \
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srl %idreg, 0x1c, %idreg; \
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sll %idreg, 0x02, %idreg; \
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.previous; \
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sethi %hi(current_set), %dest_reg; \
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or %dest_reg, %lo(current_set), %dest_reg;\
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ld [%idreg + %dest_reg], %dest_reg;
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#else
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#define LOAD_CURRENT(dest_reg, idreg) \
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sethi %hi(current_set), %idreg; \
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ld [%idreg + %lo(current_set)], %dest_reg;
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#endif
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#endif /* !(_SPARC_WINMACRO_H) */
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