68 lines
2.7 KiB
C
68 lines
2.7 KiB
C
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_CACHE_H
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#define _ASM_TILE_CACHE_H
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#include <arch/chip.h>
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/* bytes per L1 data cache line */
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#define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE()
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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/* bytes per L2 cache line */
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#define L2_CACHE_SHIFT CHIP_L2_LOG_LINE_SIZE()
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#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)
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#define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)
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/*
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* TILEPro I/O is not always coherent (networking typically uses coherent
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* I/O, but PCI traffic does not) and setting ARCH_DMA_MINALIGN to the
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* L2 cacheline size helps ensure that kernel heap allocations are aligned.
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* TILE-Gx I/O is always coherent when used on hash-for-home pages.
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*
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* However, it's possible at runtime to request not to use hash-for-home
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* for the kernel heap, in which case the kernel will use flush-and-inval
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* to manage coherence. As a result, we use L2_CACHE_BYTES for the
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* DMA minimum alignment to avoid false sharing in the kernel heap.
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*/
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#define ARCH_DMA_MINALIGN L2_CACHE_BYTES
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/* use the cache line size for the L2, which is where it counts */
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#define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT
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#define SMP_CACHE_BYTES L2_CACHE_BYTES
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#define INTERNODE_CACHE_SHIFT L2_CACHE_SHIFT
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#define INTERNODE_CACHE_BYTES L2_CACHE_BYTES
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/* Group together read-mostly things to avoid cache false sharing */
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#define __read_mostly __attribute__((__section__(".data..read_mostly")))
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/*
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* Originally we used small TLB pages for kernel data and grouped some
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* things together as "write once", enforcing the property at the end
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* of initialization by making those pages read-only and non-coherent.
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* This allowed better cache utilization since cache inclusion did not
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* need to be maintained. However, to do this requires an extra TLB
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* entry, which on balance is more of a performance hit than the
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* non-coherence is a performance gain, so we now just make "read
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* mostly" and "write once" be synonyms. We keep the attribute
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* separate in case we change our minds at a future date.
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*/
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#define __write_once __read_mostly
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/* __ro_after_init is the generic name for the tile arch __write_once. */
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#define __ro_after_init __read_mostly
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#endif /* _ASM_TILE_CACHE_H */
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