510 lines
12 KiB
C
510 lines
12 KiB
C
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_IO_H
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#define _ASM_TILE_IO_H
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#include <linux/kernel.h>
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#include <linux/bug.h>
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#include <asm/page.h>
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/* Maximum PCI I/O space address supported. */
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access.
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer.
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*/
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#define xlate_dev_kmem_ptr(p) p
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/*
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* Change "struct page" to physical address.
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*/
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#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
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/*
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* Some places try to pass in an loff_t for PHYSADDR (?!), so we cast it to
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* long before casting it to a pointer to avoid compiler warnings.
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*/
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#if CHIP_HAS_MMIO()
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extern void __iomem *ioremap(resource_size_t offset, unsigned long size);
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extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
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pgprot_t pgprot);
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extern void iounmap(volatile void __iomem *addr);
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#else
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#define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
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#define iounmap(addr) ((void)0)
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#endif
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#define ioremap_nocache(physaddr, size) ioremap(physaddr, size)
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#define ioremap_wc(physaddr, size) ioremap(physaddr, size)
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#define ioremap_wt(physaddr, size) ioremap(physaddr, size)
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#define ioremap_uc(physaddr, size) ioremap(physaddr, size)
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#define ioremap_fullcache(physaddr, size) ioremap(physaddr, size)
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#define mmiowb()
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/* Conversion between virtual and physical mappings. */
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#define mm_ptov(addr) ((void *)phys_to_virt(addr))
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#define mm_vtop(addr) ((unsigned long)virt_to_phys(addr))
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#if CHIP_HAS_MMIO()
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/*
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* We use inline assembly to guarantee that the compiler does not
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* split an access into multiple byte-sized accesses as it might
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* sometimes do if a register data structure is marked "packed".
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* Obviously on tile we can't tolerate such an access being
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* actually unaligned, but we want to avoid the case where the
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* compiler conservatively would generate multiple accesses even
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* for an aligned read or write.
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*/
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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return *(const volatile u8 __force *)addr;
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}
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 ret;
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asm volatile("ld2u %0, %1" : "=r" (ret) : "r" (addr));
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barrier();
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return le16_to_cpu(ret);
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}
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 ret;
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/* Sign-extend to conform to u32 ABI sign-extension convention. */
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asm volatile("ld4s %0, %1" : "=r" (ret) : "r" (addr));
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barrier();
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return le32_to_cpu(ret);
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}
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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u64 ret;
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asm volatile("ld %0, %1" : "=r" (ret) : "r" (addr));
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barrier();
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return le64_to_cpu(ret);
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}
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static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
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{
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*(volatile u8 __force *)addr = val;
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}
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static inline void __raw_writew(u16 val, volatile void __iomem *addr)
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{
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asm volatile("st2 %0, %1" :: "r" (addr), "r" (cpu_to_le16(val)));
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}
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static inline void __raw_writel(u32 val, volatile void __iomem *addr)
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{
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asm volatile("st4 %0, %1" :: "r" (addr), "r" (cpu_to_le32(val)));
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}
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static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
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{
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asm volatile("st %0, %1" :: "r" (addr), "r" (cpu_to_le64(val)));
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}
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/*
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* The on-chip I/O hardware on tilegx is configured with VA=PA for the
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* kernel's PA range. The low-level APIs and field names use "va" and
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* "void *" nomenclature, to be consistent with the general notion
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* that the addresses in question are virtualizable, but in the kernel
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* context we are actually manipulating PA values. (In other contexts,
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* e.g. access from user space, we do in fact use real virtual addresses
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* in the va fields.) To allow readers of the code to understand what's
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* happening, we direct their attention to this comment by using the
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* following two functions that just duplicate __va() and __pa().
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*/
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typedef unsigned long tile_io_addr_t;
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static inline tile_io_addr_t va_to_tile_io_addr(void *va)
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{
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BUILD_BUG_ON(sizeof(phys_addr_t) != sizeof(tile_io_addr_t));
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return __pa(va);
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}
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static inline void *tile_io_addr_to_va(tile_io_addr_t tile_io_addr)
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{
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return __va(tile_io_addr);
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}
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#else /* CHIP_HAS_MMIO() */
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#ifdef CONFIG_PCI
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extern u8 _tile_readb(unsigned long addr);
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extern u16 _tile_readw(unsigned long addr);
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extern u32 _tile_readl(unsigned long addr);
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extern u64 _tile_readq(unsigned long addr);
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extern void _tile_writeb(u8 val, unsigned long addr);
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extern void _tile_writew(u16 val, unsigned long addr);
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extern void _tile_writel(u32 val, unsigned long addr);
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extern void _tile_writeq(u64 val, unsigned long addr);
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#define __raw_readb(addr) _tile_readb((unsigned long)(addr))
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#define __raw_readw(addr) _tile_readw((unsigned long)(addr))
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#define __raw_readl(addr) _tile_readl((unsigned long)(addr))
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#define __raw_readq(addr) _tile_readq((unsigned long)(addr))
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#define __raw_writeb(val, addr) _tile_writeb(val, (unsigned long)(addr))
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#define __raw_writew(val, addr) _tile_writew(val, (unsigned long)(addr))
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#define __raw_writel(val, addr) _tile_writel(val, (unsigned long)(addr))
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#define __raw_writeq(val, addr) _tile_writeq(val, (unsigned long)(addr))
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#else /* CONFIG_PCI */
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/*
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* The tilepro architecture does not support IOMEM unless PCI is enabled.
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* Unfortunately we can't yet simply not declare these methods,
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* since some generic code that compiles into the kernel, but
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* we never run, uses them unconditionally.
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*/
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static inline int iomem_panic(void)
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{
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panic("readb/writeb and friends do not exist on tile without PCI");
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return 0;
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}
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static inline u8 readb(unsigned long addr)
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{
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return iomem_panic();
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}
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static inline u16 _readw(unsigned long addr)
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{
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return iomem_panic();
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}
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static inline u32 readl(unsigned long addr)
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{
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return iomem_panic();
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}
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static inline u64 readq(unsigned long addr)
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{
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return iomem_panic();
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}
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static inline void writeb(u8 val, unsigned long addr)
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{
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iomem_panic();
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}
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static inline void writew(u16 val, unsigned long addr)
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{
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iomem_panic();
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}
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static inline void writel(u32 val, unsigned long addr)
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{
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iomem_panic();
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}
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static inline void writeq(u64 val, unsigned long addr)
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{
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iomem_panic();
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}
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#endif /* CONFIG_PCI */
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#endif /* CHIP_HAS_MMIO() */
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#define readb __raw_readb
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#define readw __raw_readw
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#define readl __raw_readl
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#define readq __raw_readq
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#define writeb __raw_writeb
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#define writew __raw_writew
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#define writel __raw_writel
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#define writeq __raw_writeq
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#define readb_relaxed readb
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#define readw_relaxed readw
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#define readl_relaxed readl
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#define readq_relaxed readq
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#define writeb_relaxed writeb
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#define writew_relaxed writew
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#define writel_relaxed writel
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#define writeq_relaxed writeq
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#define ioread8 readb
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#define ioread16 readw
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#define ioread32 readl
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#define ioread64 readq
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#define iowrite8 writeb
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#define iowrite16 writew
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#define iowrite32 writel
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#define iowrite64 writeq
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#if CHIP_HAS_MMIO() || defined(CONFIG_PCI)
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static inline void memset_io(volatile void *dst, int val, size_t len)
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{
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size_t x;
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BUG_ON((unsigned long)dst & 0x3);
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val = (val & 0xff) * 0x01010101;
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for (x = 0; x < len; x += 4)
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writel(val, dst + x);
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}
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static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
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size_t len)
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{
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size_t x;
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BUG_ON((unsigned long)src & 0x3);
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for (x = 0; x < len; x += 4)
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*(u32 *)(dst + x) = readl(src + x);
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}
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static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
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size_t len)
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{
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size_t x;
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BUG_ON((unsigned long)dst & 0x3);
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for (x = 0; x < len; x += 4)
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writel(*(u32 *)(src + x), dst + x);
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}
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#endif
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#if CHIP_HAS_MMIO() && defined(CONFIG_TILE_PCI_IO)
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static inline u8 inb(unsigned long addr)
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{
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return readb((volatile void __iomem *) addr);
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}
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static inline u16 inw(unsigned long addr)
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{
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return readw((volatile void __iomem *) addr);
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}
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static inline u32 inl(unsigned long addr)
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{
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return readl((volatile void __iomem *) addr);
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}
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static inline void outb(u8 b, unsigned long addr)
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{
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writeb(b, (volatile void __iomem *) addr);
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}
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static inline void outw(u16 b, unsigned long addr)
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{
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writew(b, (volatile void __iomem *) addr);
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}
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static inline void outl(u32 b, unsigned long addr)
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{
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writel(b, (volatile void __iomem *) addr);
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}
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static inline void insb(unsigned long addr, void *buffer, int count)
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{
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if (count) {
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u8 *buf = buffer;
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do {
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u8 x = inb(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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static inline void insw(unsigned long addr, void *buffer, int count)
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{
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if (count) {
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u16 *buf = buffer;
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do {
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u16 x = inw(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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static inline void insl(unsigned long addr, void *buffer, int count)
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{
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if (count) {
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u32 *buf = buffer;
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do {
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u32 x = inl(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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static inline void outsb(unsigned long addr, const void *buffer, int count)
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{
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if (count) {
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const u8 *buf = buffer;
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do {
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outb(*buf++, addr);
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} while (--count);
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}
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}
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static inline void outsw(unsigned long addr, const void *buffer, int count)
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{
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if (count) {
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const u16 *buf = buffer;
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do {
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outw(*buf++, addr);
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} while (--count);
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}
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}
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static inline void outsl(unsigned long addr, const void *buffer, int count)
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{
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if (count) {
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const u32 *buf = buffer;
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do {
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outl(*buf++, addr);
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} while (--count);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
extern void __iomem *ioport_map(unsigned long port, unsigned int len);
|
||
|
|
extern void ioport_unmap(void __iomem *addr);
|
||
|
|
|
||
|
|
#else
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The TilePro architecture does not support IOPORT, even with PCI.
|
||
|
|
* Unfortunately we can't yet simply not declare these methods,
|
||
|
|
* since some generic code that compiles into the kernel, but
|
||
|
|
* we never run, uses them unconditionally.
|
||
|
|
*/
|
||
|
|
|
||
|
|
static inline long ioport_panic(void)
|
||
|
|
{
|
||
|
|
#ifdef __tilegx__
|
||
|
|
panic("PCI IO space support is disabled. Configure the kernel with CONFIG_TILE_PCI_IO to enable it");
|
||
|
|
#else
|
||
|
|
panic("inb/outb and friends do not exist on tile");
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void __iomem *ioport_map(unsigned long port, unsigned int len)
|
||
|
|
{
|
||
|
|
pr_info("ioport_map: mapping IO resources is unsupported on tile\n");
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void ioport_unmap(void __iomem *addr)
|
||
|
|
{
|
||
|
|
ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u8 inb(unsigned long addr)
|
||
|
|
{
|
||
|
|
return ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u16 inw(unsigned long addr)
|
||
|
|
{
|
||
|
|
return ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u32 inl(unsigned long addr)
|
||
|
|
{
|
||
|
|
return ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void outb(u8 b, unsigned long addr)
|
||
|
|
{
|
||
|
|
ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void outw(u16 b, unsigned long addr)
|
||
|
|
{
|
||
|
|
ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void outl(u32 b, unsigned long addr)
|
||
|
|
{
|
||
|
|
ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void insb(unsigned long addr, void *buffer, int count)
|
||
|
|
{
|
||
|
|
ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void insw(unsigned long addr, void *buffer, int count)
|
||
|
|
{
|
||
|
|
ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void insl(unsigned long addr, void *buffer, int count)
|
||
|
|
{
|
||
|
|
ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void outsb(unsigned long addr, const void *buffer, int count)
|
||
|
|
{
|
||
|
|
ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void outsw(unsigned long addr, const void *buffer, int count)
|
||
|
|
{
|
||
|
|
ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void outsl(unsigned long addr, const void *buffer, int count)
|
||
|
|
{
|
||
|
|
ioport_panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* CHIP_HAS_MMIO() && defined(CONFIG_TILE_PCI_IO) */
|
||
|
|
|
||
|
|
#define inb_p(addr) inb(addr)
|
||
|
|
#define inw_p(addr) inw(addr)
|
||
|
|
#define inl_p(addr) inl(addr)
|
||
|
|
#define outb_p(x, addr) outb((x), (addr))
|
||
|
|
#define outw_p(x, addr) outw((x), (addr))
|
||
|
|
#define outl_p(x, addr) outl((x), (addr))
|
||
|
|
|
||
|
|
#define ioread16be(addr) be16_to_cpu(ioread16(addr))
|
||
|
|
#define ioread32be(addr) be32_to_cpu(ioread32(addr))
|
||
|
|
#define iowrite16be(v, addr) iowrite16(be16_to_cpu(v), (addr))
|
||
|
|
#define iowrite32be(v, addr) iowrite32(be32_to_cpu(v), (addr))
|
||
|
|
|
||
|
|
#define ioread8_rep(p, dst, count) \
|
||
|
|
insb((unsigned long) (p), (dst), (count))
|
||
|
|
#define ioread16_rep(p, dst, count) \
|
||
|
|
insw((unsigned long) (p), (dst), (count))
|
||
|
|
#define ioread32_rep(p, dst, count) \
|
||
|
|
insl((unsigned long) (p), (dst), (count))
|
||
|
|
|
||
|
|
#define iowrite8_rep(p, src, count) \
|
||
|
|
outsb((unsigned long) (p), (src), (count))
|
||
|
|
#define iowrite16_rep(p, src, count) \
|
||
|
|
outsw((unsigned long) (p), (src), (count))
|
||
|
|
#define iowrite32_rep(p, src, count) \
|
||
|
|
outsl((unsigned long) (p), (src), (count))
|
||
|
|
|
||
|
|
#define virt_to_bus virt_to_phys
|
||
|
|
#define bus_to_virt phys_to_virt
|
||
|
|
|
||
|
|
#endif /* _ASM_TILE_IO_H */
|