322 lines
8.2 KiB
C
322 lines
8.2 KiB
C
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/* Driver for Intel Xeon Phi "Knights Corner" PMU */
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#include <linux/perf_event.h>
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#include <linux/types.h>
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#include <asm/hardirq.h>
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#include "../perf_event.h"
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static const u64 knc_perfmon_event_map[] =
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{
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[PERF_COUNT_HW_CPU_CYCLES] = 0x002a,
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x0016,
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0028,
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[PERF_COUNT_HW_CACHE_MISSES] = 0x0029,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0012,
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[PERF_COUNT_HW_BRANCH_MISSES] = 0x002b,
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};
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static const u64 __initconst knc_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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/* On Xeon Phi event "0" is a valid DATA_READ */
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/* (L1 Data Cache Reads) Instruction. */
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/* We code this as ARCH_PERFMON_EVENTSEL_INT as this */
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/* bit will always be set in x86_pmu_hw_config(). */
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[ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT,
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/* DATA_READ */
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[ C(RESULT_MISS) ] = 0x0003, /* DATA_READ_MISS */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x0001, /* DATA_WRITE */
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[ C(RESULT_MISS) ] = 0x0004, /* DATA_WRITE_MISS */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0011, /* L1_DATA_PF1 */
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[ C(RESULT_MISS) ] = 0x001c, /* L1_DATA_PF1_MISS */
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},
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},
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[ C(L1I ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x000c, /* CODE_READ */
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[ C(RESULT_MISS) ] = 0x000e, /* CODE_CACHE_MISS */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0x10cb, /* L2_READ_MISS */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x10cc, /* L2_WRITE_HIT */
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x10fc, /* L2_DATA_PF2 */
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[ C(RESULT_MISS) ] = 0x10fe, /* L2_DATA_PF2_MISS */
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT,
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/* DATA_READ */
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/* see note on L1 OP_READ */
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[ C(RESULT_MISS) ] = 0x0002, /* DATA_PAGE_WALK */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x0001, /* DATA_WRITE */
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[ C(RESULT_MISS) ] = 0x0002, /* DATA_PAGE_WALK */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x000c, /* CODE_READ */
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[ C(RESULT_MISS) ] = 0x000d, /* CODE_PAGE_WALK */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0012, /* BRANCHES */
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[ C(RESULT_MISS) ] = 0x002b, /* BRANCHES_MISPREDICTED */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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};
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static u64 knc_pmu_event_map(int hw_event)
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{
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return knc_perfmon_event_map[hw_event];
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}
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static struct event_constraint knc_event_constraints[] =
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{
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INTEL_EVENT_CONSTRAINT(0xc3, 0x1), /* HWP_L2HIT */
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INTEL_EVENT_CONSTRAINT(0xc4, 0x1), /* HWP_L2MISS */
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INTEL_EVENT_CONSTRAINT(0xc8, 0x1), /* L2_READ_HIT_E */
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INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* L2_READ_HIT_M */
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INTEL_EVENT_CONSTRAINT(0xca, 0x1), /* L2_READ_HIT_S */
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INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* L2_READ_MISS */
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INTEL_EVENT_CONSTRAINT(0xcc, 0x1), /* L2_WRITE_HIT */
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INTEL_EVENT_CONSTRAINT(0xce, 0x1), /* L2_STRONGLY_ORDERED_STREAMING_VSTORES_MISS */
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INTEL_EVENT_CONSTRAINT(0xcf, 0x1), /* L2_WEAKLY_ORDERED_STREAMING_VSTORE_MISS */
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INTEL_EVENT_CONSTRAINT(0xd7, 0x1), /* L2_VICTIM_REQ_WITH_DATA */
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INTEL_EVENT_CONSTRAINT(0xe3, 0x1), /* SNP_HITM_BUNIT */
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INTEL_EVENT_CONSTRAINT(0xe6, 0x1), /* SNP_HIT_L2 */
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INTEL_EVENT_CONSTRAINT(0xe7, 0x1), /* SNP_HITM_L2 */
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INTEL_EVENT_CONSTRAINT(0xf1, 0x1), /* L2_DATA_READ_MISS_CACHE_FILL */
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INTEL_EVENT_CONSTRAINT(0xf2, 0x1), /* L2_DATA_WRITE_MISS_CACHE_FILL */
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INTEL_EVENT_CONSTRAINT(0xf6, 0x1), /* L2_DATA_READ_MISS_MEM_FILL */
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INTEL_EVENT_CONSTRAINT(0xf7, 0x1), /* L2_DATA_WRITE_MISS_MEM_FILL */
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INTEL_EVENT_CONSTRAINT(0xfc, 0x1), /* L2_DATA_PF2 */
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INTEL_EVENT_CONSTRAINT(0xfd, 0x1), /* L2_DATA_PF2_DROP */
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INTEL_EVENT_CONSTRAINT(0xfe, 0x1), /* L2_DATA_PF2_MISS */
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INTEL_EVENT_CONSTRAINT(0xff, 0x1), /* L2_DATA_HIT_INFLIGHT_PF2 */
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EVENT_CONSTRAINT_END
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};
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#define MSR_KNC_IA32_PERF_GLOBAL_STATUS 0x0000002d
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#define MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL 0x0000002e
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#define MSR_KNC_IA32_PERF_GLOBAL_CTRL 0x0000002f
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#define KNC_ENABLE_COUNTER0 0x00000001
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#define KNC_ENABLE_COUNTER1 0x00000002
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static void knc_pmu_disable_all(void)
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{
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u64 val;
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rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
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val &= ~(KNC_ENABLE_COUNTER0|KNC_ENABLE_COUNTER1);
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wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
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}
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static void knc_pmu_enable_all(int added)
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{
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u64 val;
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rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
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val |= (KNC_ENABLE_COUNTER0|KNC_ENABLE_COUNTER1);
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wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
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}
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static inline void
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knc_pmu_disable_event(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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u64 val;
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val = hwc->config;
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val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
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(void)wrmsrl_safe(hwc->config_base + hwc->idx, val);
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}
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static void knc_pmu_enable_event(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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u64 val;
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val = hwc->config;
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val |= ARCH_PERFMON_EVENTSEL_ENABLE;
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(void)wrmsrl_safe(hwc->config_base + hwc->idx, val);
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}
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static inline u64 knc_pmu_get_status(void)
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{
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u64 status;
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rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_STATUS, status);
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return status;
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}
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static inline void knc_pmu_ack_status(u64 ack)
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{
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wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL, ack);
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}
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static int knc_pmu_handle_irq(struct pt_regs *regs)
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{
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struct perf_sample_data data;
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struct cpu_hw_events *cpuc;
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int handled = 0;
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int bit, loops;
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u64 status;
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cpuc = this_cpu_ptr(&cpu_hw_events);
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knc_pmu_disable_all();
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status = knc_pmu_get_status();
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if (!status) {
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knc_pmu_enable_all(0);
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return handled;
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}
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loops = 0;
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again:
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knc_pmu_ack_status(status);
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if (++loops > 100) {
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WARN_ONCE(1, "perf: irq loop stuck!\n");
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perf_event_print_debug();
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goto done;
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}
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inc_irq_stat(apic_perf_irqs);
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for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
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struct perf_event *event = cpuc->events[bit];
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handled++;
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if (!test_bit(bit, cpuc->active_mask))
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continue;
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if (!intel_pmu_save_and_restart(event))
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continue;
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perf_sample_data_init(&data, 0, event->hw.last_period);
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if (perf_event_overflow(event, &data, regs))
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x86_pmu_stop(event, 0);
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}
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/*
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* Repeat if there is more work to be done:
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*/
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status = knc_pmu_get_status();
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if (status)
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goto again;
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done:
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/* Only restore PMU state when it's active. See x86_pmu_disable(). */
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if (cpuc->enabled)
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knc_pmu_enable_all(0);
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return handled;
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}
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PMU_FORMAT_ATTR(event, "config:0-7" );
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PMU_FORMAT_ATTR(umask, "config:8-15" );
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PMU_FORMAT_ATTR(edge, "config:18" );
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PMU_FORMAT_ATTR(inv, "config:23" );
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PMU_FORMAT_ATTR(cmask, "config:24-31" );
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static struct attribute *intel_knc_formats_attr[] = {
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&format_attr_event.attr,
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&format_attr_umask.attr,
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&format_attr_edge.attr,
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&format_attr_inv.attr,
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&format_attr_cmask.attr,
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NULL,
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};
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static const struct x86_pmu knc_pmu __initconst = {
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.name = "knc",
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.handle_irq = knc_pmu_handle_irq,
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.disable_all = knc_pmu_disable_all,
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.enable_all = knc_pmu_enable_all,
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.enable = knc_pmu_enable_event,
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.disable = knc_pmu_disable_event,
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.hw_config = x86_pmu_hw_config,
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.schedule_events = x86_schedule_events,
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.eventsel = MSR_KNC_EVNTSEL0,
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.perfctr = MSR_KNC_PERFCTR0,
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.event_map = knc_pmu_event_map,
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.max_events = ARRAY_SIZE(knc_perfmon_event_map),
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.apic = 1,
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.max_period = (1ULL << 39) - 1,
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.version = 0,
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.num_counters = 2,
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.cntval_bits = 40,
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.cntval_mask = (1ULL << 40) - 1,
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.get_event_constraints = x86_get_event_constraints,
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.event_constraints = knc_event_constraints,
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.format_attrs = intel_knc_formats_attr,
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};
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__init int knc_pmu_init(void)
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{
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x86_pmu = knc_pmu;
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memcpy(hw_cache_event_ids, knc_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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return 0;
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}
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