280 lines
6.8 KiB
C
280 lines
6.8 KiB
C
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#include <linux/perf_event.h>
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#include <linux/types.h>
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#include "../perf_event.h"
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/*
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* Not sure about some of these
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*/
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static const u64 p6_perfmon_event_map[] =
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{
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[PERF_COUNT_HW_CPU_CYCLES] = 0x0079, /* CPU_CLK_UNHALTED */
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, /* INST_RETIRED */
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, /* L2_RQSTS:M:E:S:I */
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[PERF_COUNT_HW_CACHE_MISSES] = 0x012e, /* L2_RQSTS:I */
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, /* BR_INST_RETIRED */
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[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, /* BR_MISS_PRED_RETIRED */
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[PERF_COUNT_HW_BUS_CYCLES] = 0x0062, /* BUS_DRDY_CLOCKS */
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a2, /* RESOURCE_STALLS */
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};
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static const u64 __initconst p6_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
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[ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(L1I ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */
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[ C(RESULT_MISS) ] = 0x0f28, /* L2_IFETCH:M:E:S:I */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0x0025, /* L2_M_LINES_INM */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */
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[ C(RESULT_MISS) ] = 0x0085, /* ITLB_MISS */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED */
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[ C(RESULT_MISS) ] = 0x00c5, /* BR_MISS_PRED_RETIRED */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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};
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static u64 p6_pmu_event_map(int hw_event)
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{
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return p6_perfmon_event_map[hw_event];
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}
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/*
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* Event setting that is specified not to count anything.
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* We use this to effectively disable a counter.
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*
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* L2_RQSTS with 0 MESI unit mask.
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*/
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#define P6_NOP_EVENT 0x0000002EULL
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static struct event_constraint p6_event_constraints[] =
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{
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INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
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INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
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INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
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INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
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INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
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INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
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EVENT_CONSTRAINT_END
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};
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static void p6_pmu_disable_all(void)
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{
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u64 val;
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/* p6 only has one enable register */
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rdmsrl(MSR_P6_EVNTSEL0, val);
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val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
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wrmsrl(MSR_P6_EVNTSEL0, val);
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}
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static void p6_pmu_enable_all(int added)
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{
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unsigned long val;
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/* p6 only has one enable register */
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rdmsrl(MSR_P6_EVNTSEL0, val);
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val |= ARCH_PERFMON_EVENTSEL_ENABLE;
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wrmsrl(MSR_P6_EVNTSEL0, val);
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}
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static inline void
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p6_pmu_disable_event(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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u64 val = P6_NOP_EVENT;
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(void)wrmsrl_safe(hwc->config_base, val);
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}
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static void p6_pmu_enable_event(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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u64 val;
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val = hwc->config;
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/*
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* p6 only has a global event enable, set on PerfEvtSel0
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* We "disable" events by programming P6_NOP_EVENT
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* and we rely on p6_pmu_enable_all() being called
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* to actually enable the events.
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*/
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(void)wrmsrl_safe(hwc->config_base, val);
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}
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PMU_FORMAT_ATTR(event, "config:0-7" );
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PMU_FORMAT_ATTR(umask, "config:8-15" );
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PMU_FORMAT_ATTR(edge, "config:18" );
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PMU_FORMAT_ATTR(pc, "config:19" );
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PMU_FORMAT_ATTR(inv, "config:23" );
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PMU_FORMAT_ATTR(cmask, "config:24-31" );
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static struct attribute *intel_p6_formats_attr[] = {
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&format_attr_event.attr,
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&format_attr_umask.attr,
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&format_attr_edge.attr,
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&format_attr_pc.attr,
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&format_attr_inv.attr,
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&format_attr_cmask.attr,
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NULL,
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};
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static __initconst const struct x86_pmu p6_pmu = {
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.name = "p6",
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.handle_irq = x86_pmu_handle_irq,
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.disable_all = p6_pmu_disable_all,
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.enable_all = p6_pmu_enable_all,
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.enable = p6_pmu_enable_event,
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.disable = p6_pmu_disable_event,
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.hw_config = x86_pmu_hw_config,
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.schedule_events = x86_schedule_events,
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.eventsel = MSR_P6_EVNTSEL0,
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.perfctr = MSR_P6_PERFCTR0,
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.event_map = p6_pmu_event_map,
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.max_events = ARRAY_SIZE(p6_perfmon_event_map),
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.apic = 1,
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.max_period = (1ULL << 31) - 1,
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.version = 0,
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.num_counters = 2,
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/*
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* Events have 40 bits implemented. However they are designed such
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* that bits [32-39] are sign extensions of bit 31. As such the
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* effective width of a event for P6-like PMU is 32 bits only.
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*
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* See IA-32 Intel Architecture Software developer manual Vol 3B
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*/
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.cntval_bits = 32,
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.cntval_mask = (1ULL << 32) - 1,
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.get_event_constraints = x86_get_event_constraints,
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.event_constraints = p6_event_constraints,
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.format_attrs = intel_p6_formats_attr,
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.events_sysfs_show = intel_event_sysfs_show,
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};
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static __init void p6_pmu_rdpmc_quirk(void)
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{
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if (boot_cpu_data.x86_stepping < 9) {
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/*
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* PPro erratum 26; fixed in stepping 9 and above.
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*/
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pr_warn("Userspace RDPMC support disabled due to a CPU erratum\n");
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x86_pmu.attr_rdpmc_broken = 1;
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x86_pmu.attr_rdpmc = 0;
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}
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}
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__init int p6_pmu_init(void)
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{
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x86_pmu = p6_pmu;
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switch (boot_cpu_data.x86_model) {
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case 1: /* Pentium Pro */
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x86_add_quirk(p6_pmu_rdpmc_quirk);
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break;
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case 3: /* Pentium II - Klamath */
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case 5: /* Pentium II - Deschutes */
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case 6: /* Pentium II - Mendocino */
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break;
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case 7: /* Pentium III - Katmai */
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case 8: /* Pentium III - Coppermine */
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case 10: /* Pentium III Xeon */
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case 11: /* Pentium III - Tualatin */
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break;
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case 9: /* Pentium M - Banias */
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case 13: /* Pentium M - Dothan */
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break;
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default:
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pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model);
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return -ENODEV;
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}
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memcpy(hw_cache_event_ids, p6_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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return 0;
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}
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